Fujitsu 8FX Hardware Manual page 549

MB95630H Series
[bit4:3] CS[4:3]: Clock-1 select bits (Divider m)
[bit2:0] CS[2:0]: Clock-2 select bits (Divider n)
These bits set the shift clock frequency.
The shift clock frequency (Fsck) is set by the following equation:
Fsck =
(m n + 2)
represents the machine clock frequency (MCLK).
bit4:3
Writing "00"
Writing "01"
Writing "10"
Writing "11"
bit2:0
Writing "000"
Writing "001"
Writing "010"
Writing "011"
Writing "100"
Writing "101"
Writing "110"
Writing "111"
Note:
If the standby mode wakeup function is not used, disable the I
before making the MCU transit to stop mode or watch mode.
MN702-00009-2v0-E
5
6
7
8
4
8
22
38
98
128
256
512
FUJITSU SEMICONDUCTOR LIMITED
2
CHAPTER 24 I
Details
Details
2
C bus interface operation
C BUS INTERFACE
24.7 Registers
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