Fujitsu 8FX Hardware Manual page 187

MB95630H Series
[bit3] BF: Data register full flag
With the PWC timer function in use, this bit is set to "1" when a count value is stored in the 8/16-bit
composite timer data register (Tn0DR/Tn1DR) immediately after pulse width measurement is complete.
In 8-bit operation, this bit is set to "0" when the 8/16-bit composite timer data register (Tn0DR/Tn1DR) is
read.
The 8/16-bit composite timer data register (Tn0DR/Tn1DR) holds data if this bit is set to "1". With this bit
being "1", even when the next edge is detected, the count value is not transferred to the 8/16-bit composite
timer data register (Tn0DR/Tn1DR), and the next measurement result is thus lost. Nonetheless, there is an
exception. With the F[3:0] bits in the Tn0CR0/Tn1CR0 register having been set to "0b1001", even though the
BF bit is set to "1", the "H" pulse measurement result is transferred to the 8/16-bit composite timer data
register (Tn0DR/Tn1DR), while the cycle measurement result is not transferred to the 8/16-bit composite
timer data register. Therefore, in order to perform cycle measurement, the "H" pulse measurement result must
be read before a cycle is completed. In addition, the result of "H" pulse measurement and that of cycle
measurement are lost if they are not read before the completion of the next "H" pulse.
The BF bit in the Tn0CR1 (timer n0) register is set to "0" when the Tn1DR (timer n1) register is read during
16-bit operation.
The BF bit in the Tn1CR1 (timer n1) register is set to "0" during 16-bit operation.
This bit is "0" when any timer function other than the PWC timer function is selected.
Writing a value to this bit has no effect on operation.
bit3
Reading "0"
Reading "1"
[bit2] IF: Timer reload/overflow flag
This bit detects the count value match and the counter overflow.
With the interval timer function (one-shot or continuous) or the PWM timer function (variable-cycle mode)
in use, this bit is set to "1" if the 8/16-bit composite timer data register (Tn0DR/Tn1DR) value matches the
count value.
With the PWC timer function or the input capture function in use, this bit is set to "1" if a counter overflow
occurs.
When read by the read-modify-write (RMW) type of instruction, this bit always returns "1".Writing "0" to
this bit sets it to "0".
Writing "1" to this bit has no effect on operation.
This bit becomes "0" if the PWM function (variable-cycle mode) is selected.
The IF bit in the Tn1CR1 (timer n1) register is "0" in 16-bit operation.
bit2
Reading "0"
Reading "1"
Writing "0"
Writing "1"
MN702-00009-2v0-E
Indicates that the there is no measurement data in the 8/16-bit composite timer data register
(Tn0DR/Tn1DR).
Indicates that the there is measurement data in the 8/16-bit composite timer data register (Tn0DR/
Tn1DR).
Indicates that neither timer reload nor overflow has occurred.
Indicates that the a timer reload or an overflow has occurred.
Clears this flag.
Has no effect on operation.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 11 8/16-BIT COMPOSITE TIMER
Details
Details
11.14 Registers
165