Fujitsu 8FX Hardware Manual page 489

MB95630H Series
● Start bit detection and confirmation of receive data during reception
The start bit is detected by a falling of the serial input followed by a succession of three "L"
levels after the serial data input is sampled according to the clock (BRCLK) signal provided by
the dedicated baud rate generator with the reception operation enable bit (RXE) set to "1".
When the first "H", "L", "L", "L" train is detected in a BRCLK sample, therefore, the current
bit is regarded as the start bit.
The frequency-quartered circuit is activated upon detection of the start bit and serial data is
input to the reception shift register at intervals of four periods of BRCLK.
When data is received, sampling is performed at three points of the baud rate clock (BRCLK)
and data sampling clock (DSCLK) and received data is confirmed on a majority basis when
two bits out of three match.
Figure 22.6-5 Start Bit Detection and Serial Data Input
RXE
Serial data input
(UIn)
Baud rate clock
(BRCLK)
Start bit detection
Counter divided by 4
Data sampling clock
(DSCLK)
Reception shift register
MN702-00009-2v0-E
Start bit
"H" "L" "L" "L" "L"
X 0
X
FUJITSU SEMICONDUCTOR LIMITED
22.6 Operations and Setting Procedure Example
D0 D1
1 2 3 0 1
Sampling at three points to determine "0" or "1" on a majority basis
when two bits out of three match
D0
CHAPTER 22 UART/SIO
2 3
D1
467