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MB95630H Series
7.2
Configuration
The time-base timer consists of the following blocks:
• Time-base timer counter
• Counter clear circuit
• Interval timer selector
• Time-base timer control register (TBTC)
■ Block Diagram of Time-base Timer
Time-base timer counter
F
divided by 2
CH
F
CRH
F
MCRPLL
SCM2
SCM1
SCM0
SCS2
System clock control register (SYCC)
Stops main clock oscillation or main CR clock oscillation
Time-base timer interrupt
F
CH
F
CRH
F
MCRPLL
MN702-00009-2v0-E
Figure 7.2-1 Block Diagram of Time-base Timer
1
2
3
4
5
6
7
2
2
2
2
2
2
2
SCS1
SCS0
DIV1
DIV0
Counter clear
Software watchdog timer clear
Resets
TBIF
Time-base timer control register (TBTC)
: Main clock
: Main CR clock
: Main CR PLL clock
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 7 TIME-BASE TIMER
To prescaler
8
9
10
11
12
13
14
15
2
2
2
2
2
2
2
2
Counter
Interval timer
clear circuit
TBIE
-
TBC3
TBC2
7.2 Configuration
To software watchdog timer
16
17
18
19
20
21
22
2
2
2
2
2
2
2
2
selector
TBC1
TBC0
TCLR
23
24
2
89
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