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CHAPTER 18 8/16-BIT PPG
18.6 Operations and Setting Procedure Example
Figure 18.6-2 Operation of 8-bit PPG Independent Mode
Count clock
(Cycle T)
PEN
(Counter start)
Cycle setting
m=5
(PPS)
Duty setting
n=4
(PDS)
PPG timer n0 counter value
Downcounter value matches
matches duty setting value
Counter borrow
PPG output source
PPGn0 Pin
(Normal polarity)
(Reverse polarity)
Example for setting the duty to 50%
When the PDS register is set to "0x02" with the PPS register set to "0x04", the PPG output is
set at a duty ratio of 50% (half the value of the PPS register is set to the PDS register).
314
3
5
5
4
2
1
Synchronizing with machine clock
FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
Stop
3
4
2
1
5
4
(1)
(2)
(1) = n
T
(2) = m
T
3
2
Stop
T: Count clock cycle
m: PPS register value
n: PDS register value
: The value changes depending
on the count clock selected and
the start timing.
MN702-00009-2v0-E
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