Fujitsu 8FX Hardware Manual page 225

MB95630H Series
● LIN synch break/synch field detection circuit
This circuit detects a LIN synch break when the LIN master node transmits a message header.
The LBD flag is set when the LIN synch break is detected. An internal signal is output to 8/16-
bit composite timer in order to detect the first and the fifth falling edges of the LIN synch field
and to measure the actual serial clock synchronization transmitted by the master node.
● LIN synch break generation circuit
This circuit generates a LIN synch break with a length set.
● Bus idle detection circuit
If this circuit detects that no transmission or reception is in progress, it sets the TBI flag bit or
the RBI flag bit to "1" respectively.
● LIN-UART serial control register (SCR)
Its operating functions are as follows:
• Setting the use of the parity bit
• Parity bit select
• Setting stop bit length
• Setting data length
• Selecting the frame data format in operating mode 1
• Clearing the error flag
• Enabling/disabling transmission
• Enabling/disabling reception
● LIN-UART serial mode register (SMR)
Its operating functions are as follows:
• Selecting the LIN-UART operating mode
• Selecting the clock input source
• Selecting between one-to-one connection to the external clock and connection to the reload
counter
• Resetting the dedicated reload timer
• LIN-UART software reset (maintaining register settings)
• Enabling/disabling output to the serial data pin
• Enabling/disabling output to the clock pin
● LIN-UART serial status register (SSR)
Its operating functions are as follows:
• Checking transmission/reception or error status
• Selecting the transfer direction (LSB-first or MSB-first)
• Enabling/disabling receive interrupts
• Enabling/disabling transmit interrupts
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 14 LIN-UART
14.2 Configuration
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