Operations And Setting Procedure Example - Fujitsu 8FX Hardware Manual

MB95630H Series
8.3

Operations and Setting Procedure Example

The watchdog timer generates a watchdog reset when the watchdog timer
counter overflows.
■ Operations of Watchdog Timer
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How to activate the watchdog timer
Software watchdog
• The watchdog timer is activated when "0b0101" is written to the watchdog control bits of
the watchdog timer control register (WDTC:WTE[3:0]) for the first time after a reset. The
count clock switch bits of the watchdog timer control register (WDTC:CS[1:0], CSP)
should also be set at the same time.
• Once the watchdog timer is activated, a reset is the only way to stop its operation.
Hardware watchdog
• To activate the hardware watchdog timer, write any value except "0xA596" to the addresses
0xFFBE and 0xFFBF on the Flash memory. After a reset, the data in 0xFFBE and 0xFFBF
on the Flash memory are copied to the watchdog timer selection ID register (upper/lower)
(WDTH/WDTL) (0x0FEB/0x0FEC). Writing "0xA597" to the addresses 0xFFBE and
0xFFBF on the Flash memory enables the hardware watchdog timer except in standby
modes; writing any value other than "0xA596" and "0xA597" enables the hardware
watchdog timer in all modes. See "CHAPTER 27 NON-VOLATILE REGISTER (NVR)
INTERFACE" for details of the watchdog timer selection ID.
• Start operation after a reset is released.
• CS[1:0] and CSP bits are read-only bits fixed at "0b001".
• The counter of the watchdog timer is cleared by a reset, and the watchdog timer resumes its
operation after the reset is released.
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Clearing the watchdog timer
• When the counter of the watchdog timer is not cleared within the interval time, it
overflows, allowing the watchdog timer to generate a watchdog reset.
• The counter of the hardware watchdog timer is cleared when "0b0101" is written to the
watchdog control bits of the watchdog timer control register (WDTC:WTE[3:0]). The
counter of the software watchdog timer is cleared when "0b0101" is written to the
watchdog control bits of the watchdog timer control register (WDTC:WTE[3:0]) for the
second time and from the second time onward.
• The watchdog timer is cleared at the same time as the timer selected as the count clock
(time-base timer or watch prescaler) is cleared.
●
Operation in standby mode
• In the case of activating the software watchdog timer, or starting the hardware watchdog
timer with its operation in standby mode disabled, regardless of the clock mode selected,
once the device transits to standby mode, the counter of the watchdog timer is cleared and
the watchdog timer stops its operation. When the device wakes up from standby mode, the
watchdog timer resumes its operation.
• In the case of activating the hardware watchdog timer with its operation in standby mode
enabled, whether the device transits to standby mode or wakes up from standby mode, the
counter of the watchdog timer is not cleared and the watchdog timer continues its operation.
MN702-00009-2v0-E
CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER
FUJITSU SEMICONDUCTOR LIMITED
8.3 Operations and Setting Procedure
Example
103