Main Cr Clock Trimming Register (Lower) (Crtl) - Fujitsu 8FX Hardware Manual

CHAPTER 27 NON-VOLATILE REGISTER (NVR) INTERFACE
27.3 Registers
27.3.2

Main CR Clock Trimming Register (Lower) (CRTL)

This section describes the main CR clock trimming register (lower) (CRTL).
■ Register Configuration
bit 7
Field —
Attribute —
Initial value 0
■ Register Functions
[bit7:5] Undefined bits
Their read values are always "0". Writing values to these bits has no effect on operation.
[bit4:0] CRTL[4:0]: Main CR clock fine trimming bits
The settings of these bits are loaded from the Flash address 0xFFBD (bit4:0) after a reset. Their initial values
are determined by the pre-loaded values in the NVR Flash area.
Fine trimming modifies the main CR clock frequency with a smaller step. Increasing the fine trimming value
decreases the main CR clock frequency.
bit4:0
Writing "00000"
:
Writing "11111"
See "27.4 Notes on Main CR Clock Trimming" and "27.5 Notes on Using NVR Interface" for details of
main CR clock trimming and notes on changing the main CR clock values respectively.
586
6 5
— — CRTL4
— — R/W
0 0
Highest main CR clock frequency
Lowest main CR clock frequency
FUJITSU SEMICONDUCTOR LIMITED
4 3
CRTL3 CRTL2
R/W R/W
X X
Details
:
MB95630H Series
2 1
CRTL1 CRTL0
R/W
X X
MN702-00009-2v0-E
0
R/W
X