Standby Control Register (Stbc) - Fujitsu Semiconductor Controller MB89950/950A Hardware Manual

3.7.4

Standby Control Register (STBC)

The standby control register (STBC) controls the CPU to enter to sleep mode, stop
mode, sets the pin states in stop mode, and initiates software reset.
I Standby control register (STBC)
Address Bit 7
0008 STP
H
W
R/W : Readable and writable
W : Write-only
— : Unused
X : Indeterminate
: Initial value
Figure 3.7-1 Standby control register (STBC)
Bit 6 Bit 5 Bit 4 Bit 3
SLP SPL RST —
W R/W W
Bit 2 Bit 1 Bit 0 Initial value
— — — 0001----
Software reset bi t
RST
Read
0 —
1 Reading always returns "1".
SPL Pin state specification bit
0
External pins hold their states prior to entering stop mode.
External pins go to high-impedance state on entering stop
1
mode.
SLP
Read
0 Reading always returns "0".
1 —
STP
Read
0 Reading always returns "0".
1 —
CHAPTER 3 CPU
B
Wri te
Generates a reset signal for
four instruction cycles.
No effect on operation.
Sleep bit
Wri te
No effect on operation.
Goes to sleep mode.
Stop bit
Wri te
No effect on operation.
Goes to stop mode.
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