Operations And Setting Procedure Example - Fujitsu 8FX Hardware Manual

CHAPTER 9 WATCH PRESCALER
9.4 Operations and Setting Procedure
Example
9.4

Operations and Setting Procedure Example

The watch prescaler operates as an interval timer.
■ Operations of Interval Timer Function (Watch Prescaler)
The counter of the watch prescaler continues to count down using the subclock divided by two
or the sub-CR clock divided by two as its count clock as long as the subclock or the sub-CR
clock oscillates.
When cleared (WPCR:WCLR = 1), the counter starts counting down from "0xFFFF". Once it
reaches "0x0000", it returns to "0xFFFF" to continue counting. As soon as the time set by the
interrupt interval time select bits has elapsed during the counting down, the watch prescaler
interrupt request flag bit (WPCR:WTIF) is set to "1" in any mode except the stop mode in
which the subclock mode or the sub-CR clock mode is used. In other words, a watch interrupt
request is generated at every selected interval time, based on the time when the counter was
last cleared.
■ Clearing Watch Prescaler
If the watch prescaler is cleared, other peripheral functions that are using the watch prescaler
output are affected by changes in count time and by other factors.
When clearing the counter using the watch prescaler clear bit (WPCR:WCLR), modify the
settings of other peripheral functions so that clearing the counter does not have any unexpected
effect on them.
When the output of the watch prescaler is selected as the count clock, clearing the watch
prescaler also clears the watchdog timer.
The watch prescaler is cleared not only by the watch prescaler clear bit (WPCR:WCLR) but
also when the subclock or the sub-CR clock is stopped and the oscillation stabilization wait
time is necessary. The watch prescaler is cleared in the following situations:
• The device transits from the subclock mode or sub-CR clock mode to the stop mode.
• The subclock oscillation enable bit or the sub-CR clock oscillation enable bit in the system
clock control register 2 (SYCC2:SOSCE or SCRE) is set to "0" in main clock mode, main
CR clock mode, or main CR PLL clock mode.
In addition, the counter of the watch prescaler is cleared and stops operating when a reset is
generated.
■ Input Clock Selection for Watch Prescaler
Below are the clocks selected as input clocks of the watch prescaler in different clock modes.
• In main clock mode, main CR clock mode, and main CR PLL clock mode
When the subclock oscillation is enabled and the subclock oscillation stabilization wait
time elapses, the subclock is selected as the input clock of the watch prescaler.
When the sub-CR clock oscillation is enabled and the sub-CR clock oscillation stabilization
wait time elapses, the sub-CR clock is selected as the input clock of the watch prescaler.
When the subclock oscillation and the sub-CR clock oscillation are enabled, and the
oscillation stabilization wait time elapses, the subclock is selected as the input clock of the
watch prescaler.
• In subclock mode
Only the subclock is used as the input clock of the watch prescaler.
116 FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
MN702-00009-2v0-E