Fujitsu 8FX Hardware Manual page 526

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CHAPTER 24 I C BUS INTERFACE
24.6 Operations and Setting Procedure Example
■ Start Conditions
While the bus is idle (SCLn and SDAn are both at the logical "H" level), the master generates a
start condition to start transmission. As shown in Figure 24.6-1, a start condition is triggered
when the SDAn line is changed from "H" to "L" while SCLn = "H". This starts a new data
transfer and commences master/slave operation.
A start condition can be generated in either of the following two ways.
• By writing "1" to the IBCR1n:MSS bit while the I
IBSRn:BB = 0, IBCR1n:INT = 0, and IBCR0n:ALF = 0). (Next, IBSRn:BB is set to "1" to
indicate that the bus is busy.)
• By writing "1" to the IBCR1n:SCC bit during an interrupt while in master mode
(IBCR1n:MSS = 1, IBSRn:BB = 1, IBCR1n:INT = 1, and IBCR0n:ALF = 0). (This
generates a repeated START condition.)
Writing "1" to the IBCR1n:MSS or IBCR1n:SCC bit is ignored in other than the above cases.
If another system is using the bus when "1" is written to the IBCR1n:MSS bit, the
IBCR0n:ALF bit is set to "1".
■ Addressing
● Slave addressing in master mode
In master mode, IBSRn:BB and IBSRn:TRX are set to "1" after the start condition is generated,
and the slave address in the IDDRn register is output to the bus starting with the MSB. The
address data consists of eight bits: the 7-bit slave address and the data transfer direction R/W
bit (bit0 in the IDDRn register).
The acknowledgment from the slave is received after the address data is sent. SDAn goes to
"L" in the ninth clock cycle and the acknowledge bit from the receiving device is received (See
Figure 24.6-1). In this case, the R/W bit (IDDRn:bit0) is inverted logically and stored in the
IBSRn:TRX bit as "1" if the SDAn level is "L".
● Addressing in slave mode
In slave mode, after the start condition is detected, IBSRn:BB is set to "1" and IBSRn:TRX is
set to "0", and the data received from the master is stored in the IDDRn register. After the
address data is received, the IDDRn and IAARn registers are compared. If the addresses match,
IBSRn:AAS is set to "1" and an acknowledgment is sent to the master. Next, bit0 in the receive
data (bit0 in the IDDRn register) is saved in the IBSRn:TRX bit.
■ Data Transfer
If the MCU is addressed as a slave, data can be sent or received byte by byte with the direction
determined by the R/W bit sent by the master.
Each byte to be output on the SDAn line is fixed at eight bits. As shown in Figure 24.6-1, the
receiver sends an acknowledgment to the sender by forcing the SDAn line to the stable "L"
level while the acknowledge clock pulse is "H". Data is transferred at one clock pulse per bit
with MSB at the head. Sending and receiving an acknowledgment is required after each byte is
transferred. Accordingly, nine clock pulses are required to transfer one complete data byte.
504 FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
2
C bus is not in use (IBCR1n:MSS = 0,
MN702-00009-2v0-E