Fujitsu 8FX Hardware Manual page 193

MB95630H Series
● PWM timer function (variable-cycle)
The 8/16-bit composite timer n0 data register (Tn0DR) and 8/16-bit composite timer n1 data
register (Tn1DR) are used to set "L" pulse width time and cycle respectively. When the timer
starts operating (Tn0CR1/Tn1CR1:STA = 1), the value of each register is transferred to the
latch in the 8-bit comparator and the two counters start counting from timer output "L". When
the Tn0DR value transferred to the latch matches the timer n0 counter value, the timer output
becomes "H" and the counting continues until the Tn1DR value transferred to the latch
matches the timer n1 counter value. When the Tn1DR value transferred to the latch of the 8-bit
comparator matches the timer n1 counter value, the values of the Tn0DR register and the
T01DR register are transferred again to the latch and the counter performs the next PWM cycle
of counting.
The current count value can be read from this register. In 16-bit operation, write the upper
timer data to Tn1DR and lower timer data to Tn0DR, and read Tn1DR first and then Tn0DR.
● PWC timer function
The 8/16-bit composite timer data register (Tn0DR/Tn1DR) is used to read PWC measurement
results. When PWC measurement is completed, the counter value is transferred to this register
and the BF bit is set to "1".
When the 8/16-bit composite timer data register is read, the BF bit is set to "0". While the BF
bit is "1", no data is transferred to the 8/16-bit composite timer data register.
There is an exception. With the F[3:0] bits in the Tn0CR0/Tn1CR0 register having been set to
"0b1001", even though the BF bit is set to "1", the "H" pulse measurement result is transferred
to the 8/16-bit composite timer data register, while the cycle measurement result is not
transferred to the 8/16-bit composite timer data register. Therefore, in order to perform cycle
measurement, the "H" pulse measurement result must be read before a cycle is completed. In
addition, the result of "H" pulse measurement and that of cycle measurement are lost if they are
not read before the completion of the next "H" pulse.
When reading the 8/16-bit composite timer data register, ensure that the BF bit is not cleared
accidentally.
If new data is written to the 8/16-bit composite timer data register, the stored measurement data
is replaced with the new data. Therefore, do not write data to the register. In 16-bit operation,
write the upper timer data to Tn1DR and lower timer data to Tn0DR, and read Tn1DR first and
then Tn0DR.
● Input capture function
The 8/16-bit composite timer data register (Tn0DR/Tn1DR) is used to read input capture
results. When an edge specified is detected, the counter value is transferred to the 8/16-bit
composite timer data register.
If new data is written to the 8/16-bit composite timer data register, the stored measurement data
is replaced with the new data. Therefore, do not write data to the register. In 16-bit operation,
write the upper timer data to Tn1DR and lower timer data to Tn0DR, and read Tn1DR first and
then Tn0DR.
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 11 8/16-BIT COMPOSITE TIMER
11.14 Registers
171