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IV ANALOG BLOCK: A/D CONVERTER
When a trigger is input, the A/D converter samples and A/D-converts the analog input signal, beginning with
the conversion start channel selected by CS[2:0].
Upon completion of the A/D conversion in that channel, the A/D converter stores the conversion result, in 10-
bit data registers ADD[9:0] (ADD[9:8] = D[1:0]/0x40241, ADD[7:0] = D[7:0]/0x40240), and sets the
conversion-complete flag ADF (D3) / A/D enable register (0x40244) and interrupt factor flag FADE (D0) /
Port input 4–7, clock timer and A/D interrupt factor flag register (0x40287). If multiple channels are specified
using CS[2:0] and CE[2:0], A/D conversions in the subsequent channels are performed in succession.
The ADST used for the software trigger is set to "1" during A/D conversion, even when it is started by some
other trigger, so it can be used as an A/D-conversion status bit.
The channel in which conversion is underway can be identified by reading CH[2:0] (D[2:0]) / A/D trigger
register (0x40242).
Reading out A/D conversion results
As explained earlier, the results of A/D conversion are stored in the ADD[9:0] register each time conversion
in one channel is completed. Since an interrupt can be generated simultaneously, this interrupt is normally
used to read out the converted data. In addition, be sure to reset the interrupt factor flag (by writing "0") to
prepare the A/D converter for the next operation.
Since the interrupt factor of the A/D converter can also be used to invoke DMA, the conversion results can
automatically be transferred to a specified memory location.
If multiple A/D conversion channels are specified, the conversion results in one channel must be read out
prior to completion of conversion in the next channel. If the A/D conversion currently under way is
completed before the previous conversion results are read out, the ADD[9:0] register is overwritten with the
new conversion results.
If ADD[9:0] is updated when the conversion-complete flag ADF = "1" (before the converted data is read out),
the overwrite-error flag OWE (D0) / A/D enable register (0x40244) is set to "1". The conversion-complete
flag ADF is reset to "0" when the converted data is read out. If ADD[9:0] is updated when ADF = "0", OWE
remains at "0", indicating that the operation has been completed normally. When reading out data, also read
the OWE flag also to make sure the data is valid. Once OWE is set, it remains set until it is reset to "0" in the
software. Note also that if OWE is set, ADF also is set. In this case, read out the converted data and reset
ADF.
Terminating A/D conversion
• For normal mode (MS = "1")
In the normal mode, A/D conversion is performed successively from the conversion start channel specified
using CS[2:0] to the conversion end channel specified using CE[2:0], and is completed after these
conversions are executed in one operation. ADST is reset to "0" upon completion of the conversion.
• For continuous mode (MS = "0")
In the continuous mode, A/D conversion from the conversion-start to the conversion-end channels is executed
repeatedly, without being stopped in the hardware. To terminate conversion, therefore, ADST must be reset to
"0" in the software. However, the A/D conversion being executed will be completed normally or forcibly
stopped depending on the timing of writing "0" to ADST. When the A/D conversion has completed normally,
ADF is set to "1" and the conversion results can be obtained. If it is forcibly stopped, ADF maintains its
previous status, therefore, conversion results cannot be obtained.
• Forced termination
In the continuous mode, A/D conversion is immediately terminated by writing "0" to ADST. The results of
the conversion then under-way cannot be obtained.
In the normal mode, writing "0" to ADST cannot terminate A/D conversion.
Note that writing "0" to ADE cannot terminate the A/D conversion under-way (ADST = "1").
Note: Once A/D conversion ends, further A/D conversion will not be performed correctly if restarted
within an interval shorter than one cycle of the A/D converter operating clock set by the prescaler.
B-IV-2-6
EPSON
S1C33L03 FUNCTION PART
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