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VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
I/O Pins and Connection
I/O Pins
Table 2.1 lists the pins used for the SDRAM interface.
Pin name
A[13:12]/SDA[12:11],
A[10:1]/SDA[9:0]
A[15:14]/SDBA[1:0]
D[15:0]
#CE8/#RAS1/#CE14/#RAS3/#SDCE1
#CE7/#RAS0/#CE13/#RAS2/#SDCE0
#HCAS/#SDCAS
#LCAS/#SDRAS
BCLK/SDCLK
P20/#DRD/SDCKE
P21/#DWE/#GAAS/#SDWE
P33/#DMAACK1/SIN3/SDA10
P32/#DMAACK0/#SRDY3/HDQM
P15/EXCL4/#DMAEND0/#SCLK3/
LDQM
Connection Examples
Figures 2.2 and 2.3 show examples of how to connect 16-bit SDRAMs to the S1C33. Figure 2.4 shows an example
of how to connect an 8-bit SDRAM to the S1C33.
SDA[12:11](A[13:12])
SDBA[1:0](A[15:14])
#SDCE0/1(#CE7/8)
B-VI-2-2
Table 2.1 I/O Pin List
I/O
O Address bus
O SDRAM bank select signals
I/O Data bus (D0–D15)
O Area 8/14 chip enable / DRAM Row strobe / SDRAM chip enable 1
O Area 7/13 chip enable / DRAM Row strobe / SDRAM chip enable 0
O DRAM column address strobe (High-byte) / SDRAM column address
strobe
O DRAM column address strobe (Low-byte) / SDRAM row address strobe
O Bus clock output / SDRAM operating clock
I/O I/O port / DRAM read / SDRAM clock enable
I/O I/O port / DRAM write (Low-byte) / Area address strobe output for GA /
SDRAM write
I/O I/O port / HSDMA Ch. 1 acknowledge output / Serial I/F Ch. 3 data input /
SDRAM address bus 10
I/O I/O port / HSDMA Ch. 0 acknowledge output / Serial I/F Ch. 3 ready signal
output / SDRAM data (High-byte) input/output mask signal output
I/O I/O port / 16-bit timer 4 event counter input / HSDMA Ch. 0 end-of-transfer
signal output / Serial I/F Ch. 3 clock input/output / SDRAM data (Low-byte)
input/output mask signal output
S1C33
SDA10(P33)
SDA[9:0](A[10:1])
D[15:0]
BCLK
SDCKE(P20)
#SDCAS(#HCAS)
#SDRAS(#LCAS)
#SDWE(P21)
HDQM(P32)
LDQM(P15)
Figure 2.2 Connecting a 16-bit SDRAM (32MB)
Function
256M SDRAM
(4M x 16 bits x 4 banks)
A[12:11]
A10
A[9:0]
BA[1:0]
DQ[15:0]
CLK
CKE
#CS
#CAS
#RAS
#WE
DQMU
DQML
EPSON
S1C33L03 FUNCTION PART
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