Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 47

Register name Address Bit
Key input, 0040270 D7–6
port input 0–3 (B) D5
interrupt D4
enable register D3
D2
D1
D0
DMA interrupt 0040271 D7–5
enable register (B) D4
D3
D2
D1
D0
16-bit timer 0/1 0040272 D7
interrupt (B) D6
enable register D5–4
D3
D2
D1–0
16-bit timer 2/3 0040273 D7
interrupt (B) D6
enable register D5–4
D3
D2
D1–0
16-bit timer 4/5 0040274 D7
interrupt (B) D6
enable register D5–4
D3
D2
D1–0
8-bit timer 0040275 D7–4
interrupt (B) D3
enable register D2
D1
D0
Serial I/F 0040276 D7–6
interrupt (B) D5
enable register D4
D3
D2
D1
D0
Port input 4–7, 0040277 D7–6
clock timer, (B) D5
A/D interrupt D4
enable register D3
D2
D1
D0
S1C33L03 PRODUCT PART
Name Function
– reserved
EK1 Key input 1
EK0 Key input 0
EP3 Port input 3
EP2 Port input 2
EP1 Port input 1
EP0 Port input 0
– reserved
EIDMA IDMA
EHDM3 High-speed DMA Ch.3
EHDM2 High-speed DMA Ch.2
EHDM1 High-speed DMA Ch.1
EHDM0 High-speed DMA Ch.0
E16TC1 16-bit timer 1 comparison A
E16TU1 16-bit timer 1 comparison B
– reserved
E16TC0 16-bit timer 0 comparison A
E16TU0 16-bit timer 0 comparison B
– reserved
E16TC3 16-bit timer 3 comparison A
E16TU3 16-bit timer 3 comparison B
– reserved
E16TC2 16-bit timer 2 comparison A
E16TU2 16-bit timer 2 comparison B
– reserved
E16TC5 16-bit timer 5 comparison A
E16TU5 16-bit timer 5 comparison B
– reserved
E16TC4 16-bit timer 4 comparison A
E16TU4 16-bit timer 4 comparison B
– reserved
– reserved
E8TU3 8-bit timer 3 underflow
E8TU2 8-bit timer 2 underflow
E8TU1 8-bit timer 1 underflow
E8TU0 8-bit timer 0 underflow
– reserved
ESTX1 SIF Ch.1 transmit buffer empty
ESRX1 SIF Ch.1 receive buffer full
ESERR1 SIF Ch.1 receive error
ESTX0 SIF Ch.0 transmit buffer empty
ESRX0 SIF Ch.0 receive buffer full
ESERR0 SIF Ch.0 receive error
– reserved
EP7 Port input 7
EP6 Port input 6
EP5 Port input 5
EP4 Port input 4
ECTM Clock timer
EADE A/D converter
EPSON
4 PERIPHERAL CIRCUITS
Setting Init. R/W
– –
1 Enabled 0 Disabled 0
0
0
0
0
0
– –
1 Enabled 0 Disabled 0
0
0
0
0
1 Enabled 0 Disabled 0
0
– –
1 Enabled 0 Disabled 0
0
– –
1 Enabled 0 Disabled 0
0
– –
1 Enabled 0 Disabled 0
0
– –
1 Enabled 0 Disabled 0
0
– –
1 Enabled 0 Disabled 0
0
– –
– –
1 Enabled 0 Disabled 0
0
0
0
– –
1 Enabled 0 Disabled 0
0
0
0
0
0
– –
1 Enabled 0 Disabled 0
0
0
0
0
0
A-1
Remarks
– 0 when being read.
R/W
R/W
A-4
R/W
R/W
R/W
R/W
– 0 when being read.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
– 0 when being read.
R/W
R/W
– 0 when being read.
R/W
R/W
– 0 when being read.
R/W
R/W
– 0 when being read.
R/W
R/W
– 0 when being read.
R/W
R/W
– 0 when being read.
– 0 when being read.
R/W
R/W
R/W
R/W
– 0 when being read.
R/W
R/W
R/W
R/W
R/W
R/W
– 0 when being read.
R/W
R/W
R/W
R/W
R/W
R/W
A-31