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SRAM read cycle
1) 3.3 V/5.0 V dual power source
(Unless otherwise specified: V
Item
Read signal delay time (2)
Read signal pulse width
Read address access time (1)
Chip enable access time (1)
Read signal access time (1)
2) 3.3 V single power source
Item
Read signal delay time (2)
Read signal pulse width
Read address access time (1)
Chip enable access time (1)
Read signal access time (1)
3) 2.0 V single power source
Item
Read signal delay time (2)
Read signal pulse width
Read address access time (1)
Chip enable access time (1)
Read signal access time (1)
SRAM write cycle
1) 3.3 V/5.0 V dual power source
(Unless otherwise specified: V
Item
Write signal delay time (2)
Write signal pulse width
2) 3.3 V single power source
Item
Write signal delay time (2)
Write signal pulse width
3) 2.0 V single power source
Item
Write signal delay time (2)
Write signal pulse width
S1C33L03 PRODUCT PART
=5.0V 0.5V, V
DDE
Symbol
t
RDD2
t
t
RDW
CYC
t
ACC1
t
CEAC1
t
RDAC1
(Unless otherwise specified: V
Symbol
t
RDD2
t
t
RDW
CYC
t
ACC1
t
CEAC1
t
RDAC1
(Unless otherwise specified: V
Symbol
t
RDD2
t
t
RDW
CYC
t
ACC1
t
CEAC1
t
RDAC1
=5.0V 0.5V, V
DDE
Symbol
t
WRD2
t
t
WRW
CYC
(Unless otherwise specified: V
Symbol
t
WRD2
t
t
WRW
CYC
(Unless otherwise specified: V
Symbol
t
WRD2
t
t
WRW
CYC
EPSON
8 ELECTRICAL CHARACTERISTICS
=2.7V to 3.6V, V
DD
SS
Min.
Max.
(0.5+WC)-8
t
(1+WC)-20
CYC
t
(1+WC)-20
CYC
t
(0.5+WC)-20
CYC
=V
=2.7V to 3.6V, V
DDE
DD
SS
Min.
Max.
(0.5+WC)-10
t
(1+WC)-25
CYC
t
(1+WC)-25
CYC
t
(0.5+WC)-25
CYC
=V
=2.0V 0.2V, V
DDE
DD
SS
Min.
Max.
(0.5+WC)-10
t
(1+WC)-60
CYC
t
(1+WC)-60
CYC
t
(0.5+WC)-60
CYC
=2.7V to 3.6V, V
DD
SS
Min.
Max.
(1+WC)-10
=V
=2.7V to 3.6V, V
DDE
DD
SS
Min.
Max.
(1+WC)-10
=V
=2.0V 0.2V, V
DDE
DD
SS
Min.
Max.
(1+WC)-20
=0V, Ta=-40°C to +85°C)
Unit
8
ns
ns
ns
ns
ns
=0V, Ta=-40°C to +85°C)
Unit
10
ns
ns
ns
ns
ns
=0V, Ta=-40°C to +85°C)
Unit
10
ns
ns
ns
ns
ns
=0V, Ta=-40°C to +85°C)
Unit
8
ns
ns
=0V, Ta=-40°C to +85°C)
Unit
10
ns
ns
=0V, Ta=-40°C to +85°C)
Unit
20
ns
ns
A-81
A-1
A-8
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