Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 567

Register name Address Bit
Screen 1 039FFF3 D7–2
vertical size (B) D1
register 1 D0
FIFO control 039FFF4 D7
register (B) D6
D5
D4
D3
D2
D1
D0
Look-up table 039FFF5 D7–4
address (B) D3
register D2
D1
D0
Look-up table 039FFF7 D7
data register (B) D6
D5
D4
D3–0
GPIO 039FFF8 D7–3
configuration (B) D2
register D1
D0
GPIO 039FFF9 D7
status/control (B) D6
register D5
D4
D3
D2
D1
D0
Scratch pad 039FFFA D7
register (B) D6
D5
D4
D3
D2
D1
D0
Portrait mode 039FFFB D7
register (B) D6
D5–2
D1
D0
Line byte 039FFFC D7
count register (B) D6
for portrait D5
mode D4
D3
D2
D1
D0
S1C33L03 FUNCTION PART
Name Function
– reserved
S1VSIZE9 Screen 1 vertical size
S1VSIZE8 (high-order 2 bits)
– reserved
FIFOEO3 FIFO empty offset
FIFOEO2
FIFOEO1
FIFOEO0
LCLKSEL2 LCDC clock select
LCLKSEL1
LCLKSEL0
– reserved
LUTADDR3 Look-up table address
LUTADDR2
LUTADDR1
LUTADDR0
LUTDT3 Look-up table data
LUTDT2
LUTDT1
LUTDT0
– reserved
– reserved
GPIO2C GPIO2 configuration
GPIO1C GPIO1 configuration
GPIO0C GPIO0 configuration
– reserved
GPO6D GPO6 data
GPO5D GPO5 data
GPO4D GPO4 data
GPO3D GPO3 data
GPIO2D GPIO2 data
GPIO1D GPIO1 data
GPIO0D GPIO0 data
SP1A7 Scratch pad
SP1A6
SP1A5
SP1A4
SP1A3
SP1A2
SP1A1
SP1A0
PMODEN Portrait mode enable
PMODSEL Portrait mode select
– reserved
PMODCLK1 Portrait mode clock select
PMODCLK0 (LCDC clock division ratio)
Division ratio 1: Default mode
Division ratio 2: Alternate mode
P: Pixel clock, M: Memory clock
PMODLBC7 Line byte count
PMODLBC6
PMODLBC5
PMODLBC4
PMODLBC3
PMODLBC2
PMODLBC1
PMODLBC0
EPSON
VII LCD CONTROLLER BLOCK: LCD CONTROLLER
Setting
–
–
Fix at 8 (0b1000)
LCLKSEL[2:0] LCDC clock
1 1 1 BCU_CLK/4
1 1 0 BCU_CLK/3
1 0 1 BCU_CLK/2
1 0 0 BCU_CLK
0 1 1 reserved
0 1 0 Stop
0 0 1 Stop
0 0 0 Stop
–
–
–
1 Output 0 Input
1 Output 0 Input
1 Output 0 Input
–
1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
1 High 0 Low
1 Portrait 0 Landscape
1 Alternate 0 Default
–
PMODCLK[1:0] Division ratio 1
1 1 P: 1/8, M: 1/8
1 0 P: 1/4, M: 1/4
0 1 P: 1/2, M: 1/2
0 0 P: 1/1, M: 1/1
PMODCLK[1:0] Division ratio 2
1 1 P: 1/8, M: 1/4
1 0 P: 1/4, M: 1/2
0 1 P: 1/2, M: 1/1
0 0 P: 1/2, M: 1/1
Init. R/W Remarks
– – 0 when being read.
0 R/W
0
– – 0 when being read.
0 R/W
0
0
0
0 R/W
0
0
– – 0 when being read.
0 R/W
0
0
0
0 R/W
0
0
0
– – 0 when being read.
– – 0 when being read.
0 R/W
0 R/W
0 R/W
– – 0 when being read.
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0
0
0
0
0
0
0
0 R/W
0 R/W
– – 0 when being read.
0 R/W
0
0 R/W
0
0
0
0
0
0
0
B-VII-2-33
A-1
B-VII
LCDC