Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 616

APPENDIX: I/O MAP
Register name Address Bit
High-speed 0048228 DF
DMA Ch.0 (HW) DE
low-order DD
destination DC
address set-up DB
register DA
D9
Note:
D8
D) Dual address
D7
mode
D6
S) Single
D5
address
D4
mode
D3
D2
D1
D0
High-speed 004822A DF
DMA Ch.0 (HW) DE
high-order
destination
address set-up
register DD
DC
Note:
D) Dual address
mode
S) Single
DB
address
DA
mode
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
High-speed 004822C DF–1
DMA Ch.0 (HW)
enable register D0
High-speed 004822E DF–1
DMA Ch.0 (HW)
trigger flag D0
register
B-APPENDIX-36
Name Function
D0ADRL15 D) Ch.0 destination address[15:0]
D0ADRL14 S) Invalid
D0ADRL13
D0ADRL12
D0ADRL11
D0ADRL10
D0ADRL9
D0ADRL8
D0ADRL7
D0ADRL6
D0ADRL5
D0ADRL4
D0ADRL3
D0ADRL2
D0ADRL1
D0ADRL0
D0MOD1 Ch.0 transfer mode
D0MOD0
D0IN1 D) Ch.0 destination address
D0IN0 control
S) Invalid
D0ADRH11 D) Ch.0 destination
D0ADRH10 address[27:16]
D0ADRH9 S) Invalid
D0ADRH8
D0ADRH7
D0ADRH6
D0ADRH5
D0ADRH4
D0ADRH3
D0ADRH2
D0ADRH1
D0ADRH0
– reserved
HS0_EN Ch.0 enable
– reserved
HS0_TF Ch.0 trigger flag clear (writing)
Ch.0 trigger flag status (reading)
Setting
D0MOD[1:0] Mode
1 1 Invalid
1 0 Block
0 1 Successive
0 0 Single
D0IN[1:0] Inc/dec
1 1 Inc.(no init)
1 0 Inc.(init)
0 1 Dec.(no init)
0 0 Fixed
–
1 Enable 0 Disable
–
1 Clear 0 No operation
1 Set 0 Cleared
EPSON
Init. R/W Remarks
X R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0 R/W
0
0 R/W
0
X R/W
X
X
X
X
X
X
X
X
X
X
X
– – Undefined in read.
0 R/W
– – Undefined in read.
0 R/W
S1C33L03 FUNCTION PART