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II CORE BLOCK: ITC (Interrupt Controller)
Register name
Address
Bit
16-bit timer 4/5
0040274
D7
interrupt
(B)
D6
enable register
D5–4
D3
D2
D1–0
8-bit timer
0040275
D7–4
interrupt
(B)
D3
enable register
D2
D1
D0
Serial I/F
0040276
D7–6
interrupt
(B)
D5
enable register
D4
D3
D2
D1
D0
Port input 4–7,
0040277
D7–6
clock timer,
(B)
D5
A/D interrupt
D4
enable register
D3
D2
D1
D0
Key input,
0040280
D7–6
port input 0–3
(B)
D5
interrupt factor
D4
flag register
D3
D2
D1
D0
DMA interrupt
0040281
D7–5
factor flag
(B)
D4
register
D3
D2
D1
D0
16-bit timer 0/1
0040282
D7
interrupt factor
(B)
D6
flag register
D5–4
D3
D2
D1–0
16-bit timer 2/3
0040283
D7
interrupt factor
(B)
D6
flag register
D5–4
D3
D2
D1–0
16-bit timer 4/5
0040284
D7
interrupt factor
(B)
D6
flag register
D5–4
D3
D2
D1–0
8-bit timer
0040285
D7–4
interrupt factor
(B)
D3
flag register
D2
D1
D0
Serial I/F
0040286
D7–6
interrupt factor
(B)
D5
flag register
D4
D3
D2
D1
D0
B-II-5-14
Name
Function
E16TC5
16-bit timer 5 comparison A
E16TU5
16-bit timer 5 comparison B
–
reserved
E16TC4
16-bit timer 4 comparison A
E16TU4
16-bit timer 4 comparison B
–
reserved
–
reserved
E8TU3
8-bit timer 3 underflow
E8TU2
8-bit timer 2 underflow
E8TU1
8-bit timer 1 underflow
E8TU0
8-bit timer 0 underflow
–
reserved
ESTX1
SIF Ch.1 transmit buffer empty
ESRX1
SIF Ch.1 receive buffer full
ESERR1
SIF Ch.1 receive error
ESTX0
SIF Ch.0 transmit buffer empty
ESRX0
SIF Ch.0 receive buffer full
ESERR0
SIF Ch.0 receive error
–
reserved
EP7
Port input 7
EP6
Port input 6
EP5
Port input 5
EP4
Port input 4
ECTM
Clock timer
EADE
A/D converter
–
reserved
FK1
Key input 1
FK0
Key input 0
FP3
Port input 3
FP2
Port input 2
FP1
Port input 1
FP0
Port input 0
–
reserved
FIDMA
IDMA
FHDM3
High-speed DMA Ch.3
FHDM2
High-speed DMA Ch.2
FHDM1
High-speed DMA Ch.1
FHDM0
High-speed DMA Ch.0
F16TC1
16-bit timer 1 comparison A
F16TU1
16-bit timer 1 comparison B
–
reserved
F16TC0
16-bit timer 0 comparison A
F16TU0
16-bit timer 0 comparison B
–
reserved
F16TC3
16-bit timer 3 comparison A
F16TU3
16-bit timer 3 comparison B
–
reserved
F16TC2
16-bit timer 2 comparison A
F16TU2
16-bit timer 2 comparison B
–
reserved
F16TC5
16-bit timer 5 comparison A
F16TU5
16-bit timer 5 comparison B
–
reserved
F16TC4
16-bit timer 4 comparison A
F16TU4
16-bit timer 4 comparison B
–
reserved
–
reserved
F8TU3
8-bit timer 3 underflow
F8TU2
8-bit timer 2 underflow
F8TU1
8-bit timer 1 underflow
F8TU0
8-bit timer 0 underflow
–
reserved
FSTX1
SIF Ch.1 transmit buffer empty
FSRX1
SIF Ch.1 receive buffer full
FSERR1
SIF Ch.1 receive error
FSTX0
SIF Ch.0 transmit buffer empty
FSRX0
SIF Ch.0 receive buffer full
FSERR0
SIF Ch.0 receive error
Setting
1 Enabled
0 Disabled
–
1 Enabled
0 Disabled
–
–
1 Enabled
0 Disabled
–
1 Enabled
0 Disabled
–
1 Enabled
0 Disabled
–
1 Factor is
0 No factor is
generated
generated
–
1 Factor is
0 No factor is
generated
generated
1 Factor is
0 No factor is
generated
generated
–
1 Factor is
0 No factor is
generated
generated
–
1 Factor is
0 No factor is
generated
generated
–
1 Factor is
0 No factor is
generated
generated
–
1 Factor is
0 No factor is
generated
generated
–
1 Factor is
0 No factor is
generated
generated
–
–
1 Factor is
0 No factor is
generated
generated
–
1 Factor is
0 No factor is
generated
generated
EPSON
Init. R/W
Remarks
0
R/W
0
R/W
–
–
0 when being read.
0
R/W
0
R/W
–
–
0 when being read.
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
0
R/W
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
–
–
0 when being read.
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
–
–
0 when being read.
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
–
–
0 when being read.
X
R/W
X
R/W
–
–
0 when being read.
X
R/W
X
R/W
–
–
0 when being read.
X
R/W
X
R/W
–
–
0 when being read.
X
R/W
X
R/W
–
–
0 when being read.
X
R/W
X
R/W
–
–
0 when being read.
–
–
0 when being read.
X
R/W
X
R/W
X
R/W
X
R/W
–
–
0 when being read.
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
S1C33L03 FUNCTION PART
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