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VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
SDRAM power
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
HDQM/LDQM
SDRENA bit
SDRIS bit
SDRINI bit
SDRMRS bit
Internal #WAIT
SDA10
SDBA[1:0]
SDA[12:11, 9:0]
SDRAM Commands
The SDRAM is controlled by commands that are comprised of a combination of high or low logic level signals.
Table 2.11 lists the commands output by the SDRAM controller.
Command
Symbol
Function
Bank Active
ACTV
Bank Precharge
PRE
Precharge All
PALL
Write
WRIT
Read
READ
Mode Register Set
MRS
Deselect / NOP
NOP
Auto Refresh
REF
Self Refresh Entry
SELF
Self Refresh Exit
–
Data Write/Output
–
Enable
Data Write/Output
–
Disable
Because all of these commands are output by the SDRAM controller as necessary, they do not need to be
controlled by a user program, except for the commencement of initialization by SDRINI.
B-VI-2-14
V
CC(Min.)
NOP
PALL
MRS
H
H
Valid
Valid
Valid
100 s min.
t
RP
Figure 2.10 SDRAM Power-up and Initialization
Table 2.11 List of the Supported SDRAM Commands
DQM
Bank
SDCKE
H/LDQM
A[15:14]
H
X
V
H
X
V
H
X
X
H
X
V
H
X
V
H
X
V
H
X
X
H
X
X
H
L
X
X
L
H
X
X
H
L
X
H
H
X
EPSON
REF
REF
t
t
t
RSC
RC
RC
Pins
SDA
SDA10
A[13:12]
#SDCEx
A[10:1]
V
V
L
L
X
L
H
X
L
L
V
L
L
V
L
V
V
L
X
X
H
X
X
L
X
X
L
X
X
H
X
X
X
X
X
X
V = valid, X = don't care, L = low level, H = high level
CMD
Valid
Valid
Valid
#SDRAS
#SDCAS
#SDWE
L
H
H
L
H
L
L
H
L
H
L
L
H
L
H
L
L
L
X
X
X
L
L
H
L
L
H
X
X
X
X
X
X
X
X
X
S1C33L03 FUNCTION PART
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