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Setting preset data (initial counter value)
Each timer has an 8-bit down-counter and a reload data register. The reload data register RLDx is used to set
the initial value of the down-counter of each timer.
Timer 0 reload data: RLD0[7:0] (D[7:0]) / 8-bit timer 0 reload data register (0x40161)
Timer 1 reload data: RLD1[7:0] (D[7:0]) / 8-bit timer 1 reload data register (0x40165)
Timer 2 reload data: RLD2[7:0] (D[7:0]) / 8-bit timer 2 reload data register (0x40169)
Timer 3 reload data: RLD3[7:0] (D[7:0]) / 8-bit timer 3 reload data register (0x4016D)
Timer 4 reload data: RLD4[7:0] (D[7:0]) / 8-bit timer 4 reload data register (0x40175)
Timer 5 reload data: RLD5[7:0] (D[7:0]) / 8-bit timer 5 reload data register (0x40179)
The reload data registers can be read and written. At initial reset, the reload data registers are not initialized.
The data written to this register is preset in the down-counter, and the counter starts counting down from the
preset value.
Data is thus preset in the down-counter in the following two cases:
1. When it is preset in the software
Presetting in the software is performed using the preset control bit PSETx. When this bit is set to "1", the
content of the reload data register is loaded into the down-counter at that point.
Timer 0 preset: PSET0 (D1) / 8-bit timer 0 control register (0x40160)
Timer 1 preset: PSET1 (D1) / 8-bit timer 1 control register (0x40164)
Timer 2 preset: PSET2 (D1) / 8-bit timer 2 control register (0x40168)
Timer 3 preset: PSET3 (D1) / 8-bit timer 3 control register (0x4016C)
Timer 4 preset: PSET4 (D1) / 8-bit timer 4 control register (0x40174)
Timer 5 preset: PSET5 (D1) / 8-bit timer 5 control register (0x40178)
2. When the down-counter underflown during counting
Since the reload data is preset in the down-counter upon underflow, its underflow cycle is determined by the
value that is set in the reload data register. This underflow signal controls each function described in the
preceding section.
Before starting the 8-bit programmable timer, set the initial value in the reload data register and use the
PSETx bit to preset the data in the down-counter.
The underflow cycle is determined by the prescaler setting and the reload data. The relationship between
these two parameters is expressed by the following equation:
Under flow cycle = —————— [sec.]
f
: Prescaler input clock frequency [Hz]
PSCIN
pdr:
Prescaler division ratio set by P8TSx
RLDx: Set value of the RLDx register (0 to 255)
Timer RUN/STOP control
Each timer has a PTRUNx bit to control RUN/STOP.
Timer 0 RUN/STOP control: PTRUN0 (D0) / 8-bit timer 0 control register (0x40160)
Timer 1 RUN/STOP control: PTRUN1 (D0) / 8-bit timer 1 control register (0x40164)
Timer 2 RUN/STOP control: PTRUN2 (D0) / 8-bit timer 2 control register (0x40168)
Timer 3 RUN/STOP control: PTRUN3 (D0) / 8-bit timer 3 control register (0x4016C)
Timer 4 RUN/STOP control: PTRUN4 (D0) / 8-bit timer 4 control register (0x40174)
Timer 5 RUN/STOP control: PTRUN5 (D0) / 8-bit timer 5 control register (0x40178)
The timer is initiated to start counting down by writing "1" to PTRUNx. Writing "0" to PTRUNx disables the
clock input and causes the timer to stop counting.
This RUN/STOP control does not affect the counter data. Even when the timer has stopped counting, the
counter retains its count so that it can start counting again from that point.
When the terminal count is reached and the counter underflows, the initial value is reloaded from the reload
data register into the counter.
S1C33L03 FUNCTION PART
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
RLDx + 1
f
pdr
PSCIN
EPSON
A-1
B-III
8TM
B-III-3-5
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