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8-bit single monochrome panel timing
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
FPLINE
DRDY (MOD)
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640
For this timing diagram FPSMASK (D2/0x39FFE1) is set to "1"
VDP
= Vertical Display Period
VNDP = Vertical Non-Display Period
HDP
= Horizontal Display Period
HNDP = Horizontal Non-Display Period = (HNDP[4:0] + 4)
S1C33L03 PRODUCT PART
Line 1
Line 2
Line 3
1-1
1-9
1-2
1-10
1-3
1-11
1-4
1-12
1-5
1-13
1-6
1-14
1-7
1-15
1-8
1-16
480 panel
= LDVSIZE[9:0] + 1 (lines)
= VNDP[5:0] (lines)
= (LDHSIZE[5:0] + 1)
EPSON
8 ELECTRICAL CHARACTERISTICS
VDP
Line 4
Line 479
Line 480
HDP
LDVSIZE[9:0] (0x39FFE5, D[1:0]/0x39FFE6)
VNDP[5:0] (D[5:0]/0x39FFEA)
16 (Ts)
LDHSIZE[5:0] (D[5:0]/0x39FFE4)
8 (Ts)
HNDP[4:0] (D[4:0]/0x39FFE7)
VNDP
Line 1
Line 2
HNDP
1-633
1-634
1-635
1-636
1-637
1-638
1-639
1-640
A-99
A-1
A-8
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