Reset_N And Skitid Timing For Warm And Cold Resets; Reset_N And Sktid Timing - Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet

Figure 2-20. RESET_N and SKITID Timing for Warm and Cold Resets
FLASHROM _ CFG [1:0]
BOOTMODE[2:0]
Table 2-40. RESET_N and SKTID Timing (Sheet 1 of 2)
Parameter
T1
T2
T2
T3
T4
T5
T5
T6
T7
T8
T9
T10
70
COLD RESET
(PWR CYCLE OR PWRGOOD)
SYSCLK
RESET_N
T 1
PWRGOOD
T6
SKTID[1:0]
SKTID[2]
LRGSCLSYS
Description
PWRGOOD deasserted delay to RESET_N
asserted
PWRGOOD asserted delay to RESET_N
deasserted (Intel® Itanium® Processor 9300
Series)
PWRGOOD asserted delay to RESET_N
deasserted (Intel® Itanium® Processor 9500
Series)
RESET_N setup and hold relative to SYSCLK
asserted
RESET_N deasserted pulse width
RESET_N asserted pulse width (Intel® Itanium®
Processor 9300 Series)
RESET_N asserted pulse width (Intel® Itanium®
Processor 9500 Series)
SKTID[2:0] (as rst modifier, error) hold after
PWRGOOD deasserted
SKTID[2:0] (as socket id), LRGSCLSYS,
BOOTMODE[2:0], FLASHROM_CFG[1:0] setup to
PWRGOOD deasserted
SKTID[2:0] (as socket id), LRGSCLSYS hold
after RESET_N deasserted
SKTID[1:0] (as rst modifier) setup to RESET_N
asserted
SKTID[1:0] (as rst modifier) hold after RESET_N
asserted
WARM-STATE OR WARM -
T 3
T 2
T 4
T 7
T 8
socket id
T 11
socket id
strap value
T 13
strap values
T 14
MIN
500
200
200
® ®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
LOGIC RESETS
T 3
T9
T 10
Error Reset
(Warm-Logic) if
SKTID [ 0 ]==1
error_in
T 12
T 13
strap values
MAX UNIT
0 200
10
15
SYSCLK
8
cycles
10
15
0
0
0
ns
ms
ms
ps
ms
ms
ns
ns
ns
ns
ns