Processor Abstraction Layer; Mixing Processors Of Different Frequencies And Cache Sizes; Terminology - Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet

Description
Memory patrolling
Memory migration
Support for mixing of x4 and x8 on the
same DDR channel
Online/Offline CPU (OS assisted)
Online/Offline Memory (OS assisted)
Online/Offline I/O Hub
Thermal Design Power (TDP) SKUs
Notes:
1. OEM responsible for specifying platform-specific retraining interval.
2. Electrical isolation only, no physical add/remove supported.
3. Assume spare is installed.
1.4

Processor Abstraction Layer

The Intel
require implementation-specific Processor Abstraction Layer (PAL) firmware. PAL
firmware supports processor initialization, error recovery, and other functionality. It
provides a consistent interface to system firmware and operating systems across
processor hardware implementations. The Intel
Developer's Manual, Volume 2: System Architecture, describes PAL. Platforms must
provide access to the firmware address space and PAL at reset to allow the processors
to initialize.
The System Abstraction Layer (SAL) firmware contains platform-specific firmware to
initialize the platform, boot to an operating system, and provide runtime functionality.
Further information about SAL is available in the Intel
System Abstraction Layer Specification.
1.5 Mixing Processors of Different Frequencies and
Cache Sizes
®
All Intel
9500 Series in the same system partition are required to have the same last level
cache size and identical core frequency. Mixing processors of different core frequencies,
cache sizes, and mixing Intel
Processor 9500 Series is not supported and has not been validated by Intel. Operating
system support for multiprocessing with mixed components should also be considered.
1.6

Terminology

In this document, "the processor" refers to the Intel
and/or Intel
An '_N' notation after a signal name refers to an active low signal. This means that a
signal is in the active state (based on the name of the signal) when driven to a low
level. For example, when RESET_N is low, a processor reset has been requested. When
NMI is high, a non-maskable interrupt has occurred. In the case of lines where the
name does not imply an active state but describes part of a binary sequence (such as
20
®
Intel Itanium
Not Supported
130W, 155W, 185W
® ®
Itanium Processor 9300 Series and Intel
®
Itanium Processor 9300 Series processors and Intel
®
Itanium
® ®
Itanium Processor 9500 Series, unless otherwise indicated.
®
Processor 9300 Intel
Series
Supported
Supported
Supported
Supported
Supported
®
Itanium
®
Itanium
®
Itanium
®
Processor 9300 Series with Intel
®
Itanium
® ®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Introduction
® ®
Itanium Processor 9500
Series
Supported
Supported
Supported
Supported
Supported
Supported
130W and 170W
®
Processor 9500 Series
®
Architecture Software
®
Processor Family
® ®
Itanium Processor
®
Itanium
®
Processor 9300 Series
®