Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet page 164

Table 7-1. Signal Definitions for the Intel
Itanium
Name
SPDCLK
SPDDAT
SVID_CLK
SVID_DATIO
SVID_ALERT_N
SYSCLK/SYSCLK_N
SYSUTST_REFCLK/
SYSUTST_REFCLK_N
TCK
TDI
TDO
TESTHI[1]
TESTHI[2]
TESTHI[4]
THERMALERT_N
THERMTRIP_N
TMS
TRIGGER[1:0]
TRST_N
VCC33_SM
164
®
9500 Series (Sheet 6 of 8)
Type
I/O This is a bi-directional clock signal between the processor, DRAM SPD registers and
external components on the board. This is an open drain signal. The Intel
®
Itanium Processor 9300 Series and 9500 Series Processors are Master only; refer
®
to the Intel Itanium
Intel ® Itanium
I/O This is a bi-directional data signal between the processor, DRAM SPD registers and
external components on the board. This is an open drain signal. Intel
Processor 9300 Series and 9500 Series Processors are Master only; refer to the
®
Intel Itanium
®
Itanium Processor 9500 Series External Design Specification for limitations.
O This a source-synchronous clock used by the processor to transmit voltage ID data
to the Ararat II voltage regulator. This is an open drain signal. See Ararat II Voltage
Regulator Module Design Guide for termination requirements for the Intel
Itanium ® 9500 Processor Series.
I/0 This is a bi-directional data signal between the Intel
Series and the Ararat II voltage regulator. This is an open drain signal. See Ararat II
Voltage Regulator Module Design Guide for termination requirements for the Intel
®
Itanium 9500 Processor Series.
I This is an asynchronous signal driven by the Ararat II voltage regulator to indicate
the need to read the status register. See Ararat II Voltage Regulator Design Guide
for termination requirements for the Intel
I The differential clock pair SYSCLK/SYSCLK_N provides the fundamental clock
source for the processor. All processor link agents must receive these signals to
drive their outputs and latch their inputs. All external timing parameters are
specified with respect to the rising edge of SYSCLK crossing the falling edge of
SYSCLK_N. This differential clock pair should not be asserted until VCCA, VCCIO,
VCC33_SM, and VCC (12 V Ararat) are stabilized.
I These serve as reference clocks for the processor socket logic analyzer interposer
device during debug. It is not used by the processor, and is not connected internally
to the die. Electrical specifications on these clocks are identical to SYSCLK/
SYSCLK_N.
I Test Clock (TCK) provides the clock input for the processor TAP.
I Test Data In (TDI) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
O Test Data Out (TDO) transfers serial test data out of the processor. TDO provides
the serial output needed for JTAG specification support.
I This pin must be tied to VCCIO using a 50 ohm resistor.
I This pin must be tied to VCCIO using a 50 ohm resistor.
I This pin must be tied to VCCIO using a 5k ohm resistor.
O Thermal Alert (THERMALERT_N) is an output signal and is asserted when the on-die
thermal sensors readings exceed a pre-programmed threshold.
O The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. Thermal Trip will activate at a temperature that is significantly
above the maximum case temperature (TCASE) to ensure that there are no false
trips. Once activated, the processor will stop all execution and the signal remains
latched until RESET_N goes active. There is no hysteresis built into the thermal
sensor itself; as long as the die temperature drops below the trip level, a RESET_N
pulse will reset the processor and execution will continue. If the temperature has
not dropped below the trip level, the processor will continue to drive THERMTRIP_N
and remain stopped.
I Test Mode Select (TMS) is a JTAG specification support signal used by debug tools.
I TRIGGER[1:0] pins are needed for XDP connectivity.
I Test Reset (TRST_N) resets the TAP logic. TRST_N must be driven electrically low
during power on Reset.
I VCC33_SM is a 3.3 V supply to the processor package, required for the PIROM
interface on the processor package and also Flash device. This pin must be routed
to a 3.3 V supply.
® Itanium ® Processor 9300 Series and Intel
Description
®
Processor 9300 Series External Design Specification or
® Processor 9500 Series External Design Specification for limitations.
®
Processor 9300 Series External Design Specification or Intel
®
Itanium
® ®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Signal Definitions
®
®
® Itanium ®
®
®
® Itanium ® 9500 Processor
®
9500 Processor Series.
®