Smi Specifications For 6.4 Gt/S; Intel - Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet

Electrical Specifications
®
2.4.3

Intel

Requirements for Intel
This section defines the high-speed differential point-to-point signaling link for Intel
SMI for the Intel
and a receiver and the interconnect between them. The specifications described in this
section covers 6.4 Gb/s operation. The parameters for Intel
lower are captured in
captured in
®
Table 2-11. Intel Itanium
Values for Intel
Symbol
V Transmitter differential swing
Tx-diff-pp-pin
Z DC resistance of Tx terminations at half
TX_LOW_CM_DC
the single ended swing (which is usually
0.25*V
Z DC resistance of Rx terminations at half
RX_LOW_CM_DC
the single ended swing (which is usually
0.25*V
V Transmitter differential swing using a CLK
Tx-diff-pp-CLK-pin
like pattern
V Transmitter output DC common mode,
Tx-cm-dc-pin
defined as average of V
V Transmitter output AC common mode,
Tx-cm-ac-pin
defined as ((V
TX This is computed as absolute difference
duty-UI-pin
between average value of all UI with that
of average of odd UI, which in magnitude
would equal absolute difference between
average of all UI and average of all even
UI.
Rj value of 1-UI jitter. With X-talk off, but
TX1UI-Rj-NoXtalk-pin
on-die system like noise present. This
extraction is to be done after software
correction of DCD
pp Dj value of 1-UI jitter. With X-talk off,
TX1UI-Dj-NoXtalk--pin
but on-die system like noise present.
Rj value of N-UI jitter. With X-talk off, but
TXN-UI-Rj-NoXtalkpin
on-die system like noise present. Here 1
< N < 9.This extraction is to be done
after software correction of DCD
pp Dj value of N-UI jitter. With X-talk off,
TXN-UI-Dj-NoXtalkpin
but on-die system like noise present.
Here 1 < N < 9.Dj here indicated Djdd of
dual-dirac fitting, after software
correction of DCD
T Delay of any data lane relative to clock
Tx-data-clk-skew-pin
lane, as measured at Tx output
T Delay of any data lane relative to the
Rx-data-clk-skew-pin
clock lane, as measured at the end of Tx+
channel. This parameter is a collective
sum of effects of data clock mismatches
in Tx and on the medium connecting Tx
and Rx.
V Forward CLK Rx input voltage sensitivity
Rx-CLK
(differential pp)
® ®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
®
Itanium Processor 9500 Series Processor
® ®
Itanium Processor 9500 Series. The link consists of a transmitter
Table 2-11
Table 2-12.
®
Processor 9500 Series Transmitter and Receiver Parameter
® SMI at 6.4 GT/s and lower (Sheet 1 of 2)
Parameter
) bias point
Tx-diff-pp-pin
) bias point
Tx-diff-pp-pin
and V
D+ D-
+ V )/2 - V
D+ D- Tx-cm-dc-pin
®

SMI Specifications for 6.4 GT/s

and the PLL specification for transmit and receive are
Min Nom
800
37.4
37.4
0.9*min(VTx-
diff-pp-pin)
0.23
-0.0375
)
0
0
-0.01
0
-0.04 0.04
-0.5
-1
®
SMI at 6.4 GT/s and
Max Unit Notes
1200 mV
50
Ω
50
Ω
max(VTxdiff mV 1
-pp-pin)
0.27 Fraction of 3
V
Tx-diff-pp-
pin
0.0375 Fraction of
V
Tx-diff-pp-
pin
0.018 UI
0.008 UI 2
0.01 UI 2
0.012 UI 2
0.2 UI 2
0.5 UI
3.5 UI
150 mV
®
37