Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet page 30

Table 2-5. Intel ® Itanium
®
Intel QuickPath Interconnect and Intel SMI Channels @ 4.8 GT/s (Sheet 2 of
2)
Symbol
TX Transmitter clock or data duty cycle at the
- -
DUTY CYCLE PIN
pin. Transmit duty cycle at the pin, defined as
UI to UI jitter as specified by the Intel
Electrical Specification, Rev 1.0.
T Delay of any data lane relative to clock lane,
T - - - -
X DATA CLK SKEW PIN
as measured at Tx output
TX Peak-to-peak accumulated jitter out of any TX
- -N_UI-1E-9
ACC JIT
data or clock over 0<= n <= N UI where
N=12, measured with 1E-9 probability.
TX Transmitter clock or data UI-UI jitter at 1E-9
U -UI-1E-9
JIT I PIN
probability.
RL Transmitter Differential return loss from
TX-DIFF
50MHz to 2GHz
RL Transmitter Differential return loss from
TX-DIFF
2GHz to 4GHz
Notes:
1. Parameter value at full Intel
2. Stagger offset = 0xF.
3. See Figure 2-6.
4. The termination small signal resistance; tolerance over the entire signalling voltage range shall not exceed ±5 ohms.
5. Requires Matlab script.
®
6. Refer to Intel QuickPath Interconnect (Intel
definition is used herein, where the value of UI-UI DCD = 2*UI DCD.
7. See Figure 2-7.
8. Applies to Vtx-diff-pp-pin.
9. Peak-to-peak value of the ripple.
Table 2-6. Intel ® Itanium
QuickPath Interconnect and Intel
Symbol
R RX termination resistance
RX
T Delay of any data lane relative to the clock lane, as
Rx-data-clk-skew-pin
measured at the end of Tx+ channel. This parameter is
a collective sum of effects of data clock mismatches in
Tx and on the medium connecting Tx and Rx.
Delay of any data lane relative to the clock lane, as
measured at the end of Tx+ channel. This parameter is
T
Rx-data-clk-skew-pin
a collective sum of effects of data clock mismatches in
Tx and on the medium connecting Tx and Rx.
RL Receiver differential return loss from 50 MHz to 2 GHz
RX-DIFF
RL Receiver differential return loss from 2GHz to 4GHz
RX-DIFF
V Receiver data common mode level
Rx-data-cm-pin
V Receiver data common mode ripple
Rx-data-cm-ripple-
pin
V Receiver clock common mode level
Rx-clk-cm-pin
V Receiver clock common mode ripple
Rx-clk-cm-ripple-pin
V Minimum eye height at pin for data
RX-eye-data-pin
V Minimum eye height at pin for clk
RX-eye-clk-pin
30
® Processor 9300 Series Transmitter Parameter Values for
Parameter
®
®
QPI Refclk.
®
QPI) - Electrical Specifications for calculation of this value. Note that UI to UI.
® Processor 9300 Series Receiver Parameter Values for Intel
Parameter
Min Nom
-0.076
QPI
-0.5
0
0
-10
-6
®
SMI Channels @ 4.8 GT (Sheet 1 of 2)
Min Nom
37.4
-0.5
0.48
-10
-6
125
0
175
0
200
225
® ®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
Max Units Notes
0.076 UI-UI 6
0.5 UI 1,2
0.18 UI 5
0.17 UI 5
dB 7
dB 7
Max Units Notes
47.6 3
Ω
3.5 UI 2
0.52 UI 1
dB 6
dB 6
350 mV 2
100 mV
p-p
350 mV
100 mV
p-p
mV 4
mV 5
®