Intel - Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet

7. The FMB remote sense tolerance is ±2.5% for DC to 20 MHz at the package, where ±1.5% is allotted for a DC to 1 MHz range
and an additional ±1.0% for 1 MHz to 20 MHz. Similarly, ±6.4% is allotted for DC to 20 MHz at the die. It is expected that VCCIO
regulators meet ±1.5% at the remote sense location based on the general remote sense termination point location as described
in Figure 2-16 VR Sense Point (Representation). For future processor compatibility, it is strongly recommended that the platform
query the PIROM to assure VCCIO is set to the appropriate level prior to powering up the VCCIO supply.
8. All voltage regulation measurements taken at remote sense termination points.
9. For peak-to-peak Ripple and Noise (R&N) measured with full bandwidth (BW) of the scope (Min 1 GHz BW scope is required):
set scope diff probe and the scope at full BW (capture waveform A, channel 1).
10.For peak-to-peak Ripple and Noise (R&N) measured above 1 MHz:
Step 1 = set both: scope diff probe and/or the scope at 1 MHz BW limit (capture waveform B, channel 2)
Step 2 = calculate A-B (use scope Math function:
Table 2-19. FMB 170W and 130W Current Specifications for the Intel
9500 Series
Symbol
I I for core
CC_CORE CC
I Thermal Design Current for Core
CC_CORE_TDC
I Max Load step for core
CC_CORE_STEP
d Slew rate for core at Ararat output
ICC_CORE/dt
I I for uncore
CC_UNCORE CC
I Thermal Design Current for Uncore
CC_UNCORE_TDC
I Max Load step for uncore
CC_UNCORE_STEP
dI Slew rate for uncore at Ararat output
CC_UNCORE/dt
I I for processor I/O
CC_IO CC
d Slew rate for IO at the package pin
ICC_IO/dt
I Max Load step for max slew rate
CC_IO_STEP
T Time between steps
CC_IO_STEP
I I for processor Analog
CC_Analog CC
I I
CC33_SM CC33
Notes:
1. Values per core pair.
2. ICC_CORE_TDC is the sustained (DC equivalent) current that the processor core is capable of drawing indefinitely and should be
used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for monitoring its
temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform the processor
and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor. Please see
the Ararat II Voltage Regulator Module Design Guide for further details. The processor is capable of drawing ICC_CORE_TDC
indefinitely.
3. During system power on, the pulse inrush (ICC_CORE_STEP) can be as high as 35A peak-to-peak.
4. ICC_UNCORE_TDC is the sustained (DC equivalent) current that the processor uncore is capable of drawing indefinitely and
should be used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for
monitoring its temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform
the processor and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor.
Please see the Ararat II Voltage Regulator Module Design Guide for further details. The processor is capable of drawing
ICC_UNCORE_TDC indefinitely. This parameter is based on design characterization and is not tested.
5. During system power on, the pulse inrush (ICC_UNCORE_STEP) can be as high as 40A peak-to-peak.
6. The ICC_IO current specification applies to the total current from VCCIO pins.
7. The max load step represents the maximum current required during Intel
between steps represents the time between Intel
®
2.6.3

Intel

Cache Tolerances
2.6.3.1 Uncore Static and Transient Tolerances
Table 2-20
outputs.
44
subtract channel 1 - channel 2).
Parameter
for main supply
®
QPI and Intel
®
Itanium Processor 9300 Series Uncore, Core, and
and Figure 2-10 specify static and transient tolerances for the uncore
Max Min
35.0
30.0
14.62
34.4
80.0
75.0
30.4
168.0
17.2
54.0
5.1
4.7
4
200
® ®
QPI and Intel
®
SMI initialization.
® ®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
® ®
Itanium Processor
Units Notes
A 1
A 1, 2
A 1, 3
1
A/us
A
A 4
A 5
A/us
A 6
A/us
A 7
7
us
A
mA
SMI port initialization. The min time