Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet page 160

Table 7-1. Signal Definitions for the Intel
Itanium
Name
CSI[3:0]R[P/N]Dat[19:0],
CSI[5:4]R[P/N]Dat[9:0]
CSI[3:0]T[P/N]Dat[19:0],
CSI[5:4]T[P/N]Dat[9:0]
ERROR[0]_N
ERROR[1]_N
FBD0NBICLK[A/B][P/N]0
160
®
9500 Series (Sheet 2 of 8)
Type
I These input data signals provide means of communication between two ports via
one uni-directional transfer link (In). The RX links, are terminally ground
referenced. The ports [3:0] with [19:0] bit lanes can be configured as a full width
link with all 20 active lanes, a half width link with 10 active lanes or as a quarter
width link with five active lanes.
Intel
QuickPath
Interconnect
Interface Name
Example: CSI4RPDAT[0] represents port 5 Data, lane 0, receive signal and positive
bit of the differential pair.
O These output data signals provide means of communication between two ports via
one uni-directional transfer link (Out).The links, Tx, are terminally ground
referenced. The ports [3:0] with [19:0] bit lanes can be configured as a full width
link with 20 active lanes, a half width link with 10 active lanes or as a quarter width
link with five active lanes.
Intel
QuickPath
Interconnect
Interface Name
Example: CSI4TPDAT[0] represents port 5 Data, lane 0, transmit signal and
positive bit of the differential pair.
O Side band signaling for system management.
Refer to the Intel
9500 Series Platform Design Guide for pin considerations.
O Side band signaling for system management. Assertion on this pin indicates that an
error reset response is required from the platform.
Refer to the Intel
9500 Series Platform Design Guide for pin considerations.
I These differential pair clock signals generated from the branch zero, channel A and
B of FB-DIMMs are input to the processor.
FB-
DIMM
Interface
Name
Example: FBD0NBICLKAP0 represents FB-DIMM branch 0, northbound clock input
signal of channel A and positive bit of the differential pair.
® Itanium ® Processor 9300 Series and Intel
Description
®
5:0 R
Port Receiver
Number
®
5:0 T
Port Transmitter
Number
® Itanium ® Processor 9300 Series and Intel
® Itanium ® Processor 9300 Series and Intel
0 NB I
Branch North Input
Number Bound
® ®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Signal Definitions
P/N DAT[19:0]
Differential Lane
Pair Number
Polarity
Positive/
Negative
P/N DAT[19:0]
Differential Lane
Pair Number
Polarity
Positive/
Negative
® Itanium ® Processor
® Itanium ® Processor
CLK A/B P/N
Clock Channel Differential
Pair
Polarity
Positive/
Negative
®