Feature Data; Offset 78H/79H Definitions - Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet

Intel itanium processor quad-core 1.86-1.73 ghz with 24 mb l3 cache 9350, intel itanium processor quad-core 1.73-1.60 ghz with 20 mb l3 cache 9340, intel itanium processor quad-core 1.60-1.46 ghz with 20 mb l3 cache 9330, intel itanium processor quad-core
Hide thumbs Also See for BX80569Q9550 - Core 2 Quad 2.83 GHz Processor:
Table of Contents

Advertisement

6.4.8.2
Recommended Thermalert Hot De-assertion Hysteresis
The de-assertion threshold is expressed as the number of degrees C below the
thermalert hot threshold value in Hex format.
Example: reading offset 6Bh=00001010 and 6Ch=0000010, then programming the
CSRs with these values means THERMALERT_N will be asserted when junction
temperature rises to 10C below the PROCHOT_N (thermal throttle) threshold and will
remain asserted until the junction temperature drops to 12°C below the PROCHOT_N
threshold.
6.4.8.3
Thermal Design Power
Offset 6Dh is programmed with 2 Hex digits representing the max TDP of the part.
Example: 6Dh = 0xB9 indicates a 185 W part.
6.4.8.4
TControl
Offset 6Eh contains the recommended TControl spec in degrees C below PROCHOT_N
temperature in Hex format.
6.4.9

Feature Data

This section provides information on key features that the platform may need to
understand without powering on the processor.
6.4.9.1
Processor Core Feature Flags
For the Intel
results in EDX[31:0] from Function 1 of the CPUID instruction. These details provide
instruction and feature support by product family. These fields are RESERVED for the
®
Intel
Itanium
6.4.9.2
Package Feature Flags
Offset 78h-79h provides additional feature information from the processor. This field is
defined as follows:
Table 6-4.

Offset 78h/79h Definitions

Bit
4-32
3
2
1
0
6.4.9.3
Number of Devices in TAP Chain
At offset 7Bh, a 4-bit Hex digit is used to tell how many devices are in the TAP Chain.
The four bits are the most significant bits at this offset.
Since Intel
Series processors have one TAP per core plus a sysint TAP, this field would be set to 50h
for the Intel
156
®
®
Itanium
Processor 9300 Series, offset 72h-75h contains a copy of
®
Processor 9500 Series processor.
Reserved
Thermal calibration offset byte present
Scratch (OEM) EEPROM present (set if there is a scratch ROM at offset 80 - FFh)
Core VID present (set if there is a VID provided by the processor)
Reserved
®
Itanium
®
Processor 9300 Series and Intel
®
®
Itanium
Processor 9300 Series processor and 90 for the Intel
System Management Bus Interface
Definition
®
Itanium
®
®
Intel
Itanium
Processor 9300 Series and 9500 Series Datasheet
®
Processor 9500
®

Advertisement

Table of Contents
loading

This manual is also suitable for:

Itanium 9300 seriesItanium 9500 series

Table of Contents