Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet page 166

Table 7-1. Signal Definitions for the Intel
Itanium
Name
VR_THERMTRIP_N
VROUTPUT_ENABLE0
VRPWRGD (Ararat)
/VR_READY (Ararat II)
VSS
XDPOCPD[7:0]
XDPOCP_STRB_IN_N
XDPOCP_STRB_OUT_N
XDPOCP_FRAME_N
166
®
9500 Series (Sheet 8 of 8)
Type
I/O This signal is open drain/collector driven by Ararat Voltage Regulator into a pad at
the top of the processor package and out through a pin at the bottom of the
processor package. When asserted, it indicates that the temperature on the Ararat
solution has exceeded a critical threshold and it is required to shut down the Ararat
solution immediately. The Processor cores do not monitor or respond to this signal.
The Platform should immediately de-assert VROUTPUT_ENABLE0. If the Platform
does not respond to this signal, the Ararat Voltage Regulator is permitted to
shutdown, but should latch VR_THERMTRIP_N low, which can be reset by a power
cycle or de-assertion of VROUTPUT_ENABLE0. VR_THERMTRIP_N trip point is
determined by the Ararat Voltage Regulator Module Design and it should be set
such that VR_THERMTRIP_N is asserted prior to permanent damage to the Ararat
voltage regulator. See Ararat 170W Voltage Regulator Module Design Guide and/or
Ararat II Voltage Regulator Module Design Guide for platform requirements on
driving this signal.
I/O This signal is an input to the processor package (bottom), and drives into the Ararat
voltage regulator from the top of the package. When this signal is asserted, the
VIDs become active and the voltage regulator's startup sequence begins. When this
signal is pulled down, the Ararat Voltage regulator should shut down VCCCORE,
VCCUNCORE and VCCCACHE (Intel
Ararat 170W Voltage Regulator Module Design Guide and/or Ararat II Voltage
Regulator Module Design Guide for platform requirements on driving this signal.
I /O This signal is open drain/collector driven by Ararat Voltage Regulator into a pad at
the top of the processor package and out through a pin at the bottom of the
processor package. When pulled up (active high state), it indicates that the supply
voltages to VCCCORE, VCCUNCORE, and VCCCACHE are stable within their voltage
specification, and indicates that the Ararat VR start up sequence is completed. This
signal will transition to a logic low for power off sequencing and/or any Ararat VR
fault condition. See Ararat 170W Voltage Regulator Module Design Guide and/or
Ararat II Voltage Regulator Module Design Guide for platform requirements on pull-
up resistors and filtering.
I VSS is the ground plane for the processor.
I/O Bidirectional XDP data.
I Input clock center-aligned with XDPOCP_FRAME_N and XDPOCPD[7:0].
O Output clock edge-aligned with XDPOCP_FRAME_N and XDPOCPD[7:0].
I/O Bidirectional signal indicating valid data on XDPOCPD[7:0].
® Itanium ® Processor 9300 Series and Intel
Description
® ®
Itanium
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® ®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Signal Definitions
9300 Processor Series only). See
®