2.11.3
Power-up Voltage Sequence Timing Requirements
Table 2-39. Power-up Voltage Sequence Timing Requirements
VCC33_SM stable high to VCCA delay
VCCA to VCCIO delay time
VCCIO to PWRGOOD high delay time
VCCIO stable high to SYSCLK
SYSCLK valid before VROUTPUTENABLE0 high
VCCIO stable before VROUTPUT_ENABLE0 high for Intel
®
Itanium
VCCIO stable before VROUTPUT_ENABLE0 high for Intel
®
Itanium
VROUTPUT_ENABLE0 high to VRPWRGOOD high for Intel
®
Itanium
VROUTPUT_ENABLE0 high to VR_READY for Intel
Processor 9500 Series
VCCUNCORE time to stabilize
Delay from VCCUNCORE at programmed VID value to VCCCORE
VCCCORE steady at safe VID value
VCCCORE transition time from safe VID to programmed VID
Delay from VCCCORE/VCCUNCORE/VCCCACHE at programmed
values to VRPWRGOOD high for Intel
Series
1
VRPWRGD high to PWRGOOD high for Intel® Intel
Processor 9300 Series
VR_READY high to PWRGOOD high for Intel
9500 Series
PWRGOOD high to RESET_N high (t
Processor 9300 Series
PWRGOOD high to RESET_N high (t
Processor 9500 Series
2.12
Supported Power-down Voltage Sequence
The supported power down sequence of voltage for the processor is detailed in
Figure
2-19. It should be noted that when the processor is required to be physically
removed from its socket, power rails VCC33_SM and Vcc(12V) must also be powered
down before removal of the processor.
68
Parameter
1
Processor 9300 Series
2
Processor 9500 Series
1
Processor 9300 Series
2
1
1
®
Itanium
RESET_N
RESET_N
Min
>0
0
>0
>0
®
>1
®
>1
®
®
Itanium
®
1
1
0.05
0.05
1
0.05
®
Processor 9300
®
Itanium
®
>0
®
Itanium
®
Processor
>0
) Intel
®
Itanium
®
10
) Intel
®
Itanium
®
15
®
®
Intel
Itanium
Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
Max
Unit
μs
1000
ms
μs
μs
μs
ms
200
ms
200
ms
5
ms
8
ms
3
ms
2.5
3
ms
ms
ms
ms