Timing Relationship Between Reset_N And Sktid; Supported Power-Down Voltage Sequence Timing Requirements - Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet

Electrical Specifications
Figure 2-19. Supported Power-down Voltage Sequence Timing Requirements
R E S E T _ N
P W G O O D
V R _ O U T P U T _ E N
V ID s
V C C C O R E
V C C U N C O R E
V C C C A C H E
R E F C L K
( 1 3 3 M H z )
V C C IO
V C C A
t = 1 0 m s fo r In te l Ita n iu m 9 3 0 0 S e r ie s P r o c e s s o r
R E S E T _ N
= 1 5 m s fo r P o u ls o n - M C P r o c e s s o r
2.13

Timing Relationship Between RESET_N and SKTID

In the processor, the SKTID pins are time-shared:
SKTID[0] is interpreted as a NodeID bit during cold reset and pwrgood reset. It is
interpreted as the error reset modifier during warm-logic reset if SKTID[0] is asserted.
SKTID[2] is interpreted as a NodeID bit during cold reset and pwrgood reset, and it is
interpreted as an error input being signaled by the system at all other times (except
during non-cold resets when it is ignored).
relationship between RESET_N and SKTID pins for different reset cases.
The LRGSCLSYS pin is sampled only during the PWRGOOD and cold reset period.
The BOOTMODE[2:0] and FLASHROM_CFG[1:0] pins are sampled during the assertion
of all resets except warm-logic resets.
® ®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
t
R E S E T _ N
> = 0 u s
c h a n g e to s a fe V ID
> 1 u s
V C C A M U S T U N P O W E R A L O N G W IT H V C C IO
A s fa s t a s p o s s ib le
A ll s u p p lie s to p o w e r d o w n a s fa s t a s
P o s s ib le a fte r P W R G O O D d e a s s e r tio n
> 0 u s
Figure 2-20 and Table 2-40 show the timing
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