Intel BX80569Q9550 - Core 2 Quad 2.83 GHz Processor Datasheet page 35

Electrical Specifications
Table 2-9. Intel ® Itanium
Values for Intel
Symbol
TX
clk-acc-jit-N_UI-1E-7
TX
clk-acc-jit-N_UI-1E-9
T
Tx-data-clk-skew-pin
V
Rx-diff-pp-pin
T
Rx-diff-pp-pin
T
Rx-data-clk-skew-pin
V
Rx-CLK
V
Rx-cm-dc-pin
V
Rx-cm-ac-pin
Notes:
1. 1300 mVpp swing is recommended when CPU to CPU or CPU to IOH length is within 2" of PDG max trace
length. Note that default value is 1100 mVpp.
2. Measure AC CM noise at the TX and decimate to its spectral components. For all spectral components above
3.2 GHz, apply the attenuation of the channel at the appropriate frequency. If the resultant AC CM at the
receiver is met after taking out the appropriate spectral components meets the RX AC CM spec then we can
allow the transmitter AC CM noise to pass.
®
Table 2-10. Intel Itanium
Values for Intel
Symbol
V
Tx-diff-pp-pin
Z
TX_LOW_CM_DC
Z
RX_LOW_CM_DC
V
Tx-cm-dc-pin
® ®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
® Processor 9500 Series Transmitter and Receiver Parameter
®
QPI Channel at 4.8 GT/s (Sheet 2 of 2)
Parameter
p-p accumulated jitter out of
transmitter over 0 <= n <= N UI
where N=12, measured with 1E-7
probability.
p-p accumulated jitter out of
transmitter over 0 <= n <= N UI
where N=12, measured with 1E-9
probability.
Delay of any data lane relative to
clock lane, as measured at Tx
output
Voltage eye opening at the end of
Tx+ channel for any data or clock
channel measured with a
cumulative probability of 1E-9
(UI).
Timing eye opening at the end of
Tx+ channel for any data or clock
channel measured with a
cumulative probability of 1E-9 (UI)
Delay of any data lane relative to
the clock lane, as measured at the
end of Tx+ channel. This
parameter is a collective sum of
effects of data clock mismatches
in Tx and on the medium
connecting Tx and Rx.
Forward CLK Rx input voltage
sensitivity (differential pp)
DC common mode ranges at the
Rx input for any data or clock
channel
AC common mode ranges at the
Rx input for any data or clock
channel, defined as:
((V + V /2 - V
D+ D- RX-cm-dc-pin
®
Processor 9500 Series Transmitter and Receiver Parameter
®
QPI at 6.4 GT/s (Sheet 1 of 2)
Parameter
Transmitter differential swing
DC resistance of Tx terminations
at half the single ended swing
(which is usually 0.25*V
Tx-diff-pp-
) bias point
pin
DC resistance of Rx terminations
at half the single ended swing
(which is usually 0.25*V
Tx-diff-pp-
) bias point
pin
Transmitter output DC common
mode, defined as average of V
and V
D-
Min Nom Max
0 0.15
0 0.17
-0.5 0.5
225 1200
0.63 1
-1 3
180
125 350
-50 50
)
Min Nom Max
900 1400
37.4 50
37.4 50
0.23 0.27
D+
Unit Notes
UI
UI
UI
mV
UI
UI
mV
mV
mV 2
Unit Notes
mV 1
Ω
Ω
Fraction of 4
V
Tx-diff-pp-pin
35