Cfeb - Juniper M7I Hardware Manual

CFEB

Copyright © 2010, Juniper Networks, Inc.
The CFEB has the following major components:
Processing components:
266-MHz CPU and supporting circuitry
Integrated ASIC
33-MHz PCI bus
Storage components:
128-MB SDRAM for packet memory
128-MB SDRAM for the microkernel
8-MB SSRAM for route lookup
4-MB SSRAM for control memory
Services interfaces:
Built-in tunnel interface
Optional Adaptive Services Module
System interfaces:
100-Mbps link for internal interface to the Routing Engine
19.44-MHz reference clock—Generates clock signal for SONET/SDH PICs.
I2C controller to read the I2C/EEPROMs in the PICs and temperature sensors
I2C/EEPROM containing the serial number and revision level
Two 512-KB boot flash EPROMs (programmable on the board)
One PowerPC 8245 integrated processor
Three LEDs—A green LED labeled
MASTER indicate CFEB status.
Online/Offline button—Prepares the CFEB for removal from the router when pressed.
Ejector levers—Control the locking system that secures the CFEB in the chassis.
Chapter 2: M7i Hardware Components
, a red LED labeled
OK FAIL
, and a blue LED labeled
9