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Figure 79. Rear accessed FHFL GPUs and E3 w/o fPERC12
Table 85. Rear accessed FHFL GPUs and E3 w/o fPERC12
From
SIG_PWR_0 (signal power connector)
BP_DST_PA1 (backplane connector)
BP_DST_PB1 (backplane connector)
BP_PWR_1 (backplane power connector)
BP_DST_PA2 (backplane connector)
BP_DST_PB2 (backplane connector)
SIG_PWR_3 (signal power connector)
SL9_CPU2_PB5 (signal power connector)
SIG_PWR_4 (signal power connector)
SL3_CPU2_PB2 / SL4_CPU2_PA2 (signal power connectors) Slot3 (CPU2)
SL11_CPU1_PA6 / SL12_CPU1_PB6 (signal power
connectors)
SL7_CPU1_PB4 / SL8_CPU1_PA4 (signal power connectors)
SIG_PWR_1 (signal power connector)
SIG_PWR_2 (signal power connector)
110
Installing and removing system components
To
IO_RISER2 (CPU1) (Riser power connector)
SL6_CPU1_PB3 (signal connector on the system board)
SL5_CPU1_PA3 (signal connector on the system board)
SIG_PWR_3 (PIB power connector)
SL2_CPU2_PB1 (signal connector on the system board)
SL1_CPU2_PA1 (signal connector on the system board)
BP_PWR_1(backplane power connector)
Slot4 (CPU2)
RISER_PWR (Riser power connector)
Slot2 (CPU1)
Slot1 (CPU1)
GPU_1
GPU_2
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