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Field
Event Data 1
7:6 00 = unspecified byte 2; 10 = OEM
code in byte 2.
5:4 00 = unspecified byte 3; 10 = OEM
code in byte 3. (BIOS will not use
encodings 01 and 11 for errors
covered by this document.).
3:0... Offset from Event Trigger for
discrete event state.
Event Data 2
7:0 OEM code 2 or unspecified.
Event Data 3
7:0 OEM code 3 or unspecified.
BIOS error codes/messages
IPMI definition
The following list defines the BIOS error codes. All BIOS error codes/messages, when
encountered, appears on the video and are logged in the SEL unless it is full.
The system event log record for these BIOS error codes has a sensor type of '0F'. To
decode a BIOS error codes/message, use the last two bytes in the event description to
identify the specific error.
Code
0100
Timer Error
0103
CMOS Battery Low
0104
CMOS Settings Wrong
0105
CMOS/GPNV Checksum Bad
0106
CMOS Display Type Wrong
0108
Unlock Keyboard
0109
Keyboard Error
010A
KB/Interface Error
010B
Memory Size Decrease
010E
Cache Memory Error
0117
Pri Master Drive - ATAPI Incompatible
0118
Pri Slav e Drive - ATAPI Incompatible
0119
Sec Master Drive - ATAPI Incompatible
011A
Sec Slave Drive - ATAPI Incompatible
011B
CMOS Date/Time Not Set
011E
Cache Memory Error
0120
NVRAM cleared By jumper
0121
Password cleared By jumper
0141
PCI Memory Conflict
BIOS-specific implementation
If event data 2 and event data 3 contain OEM codes, bits
7:6 and bits 5:4 contain 10. For platforms that do not
include the POST code information with FRB-2 log, both
these fields will be 0. BIOS either should specify both
bytes or should mark both bytes as unspecified.
Byte 3:0 is 03 for FRB-2 failure during POST.
For format rev 0, if this byte is specified, it contains bits 7:0
of the POST code at the time FRB-2 reset occurred (port 80
code).
For format rev 0, if this byte is specified, it contains bits
15:8 of the PO ST code at the time FRB-2 reset occurred
(port 81 code). .If the BIOS only uses one byte POST codes,
this byte will always be zero.
Description
119
Configur ation
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