IBM xSeries 380 Hardware Maintenance Manual page 123

Spec
Offset
Version
02h 2.1+ Handle
04h 2.1+ Location
05h 2.1+ Use
06h 2.1+ Memory error
correction
07h 2.1+ Maximum
capacity
0Bh 2.1+ Memory error
information
handle
0Dh 2.1+ Number of
memory devices
Memory array — location:
Note: Enumerated values are controlled by the DMTF, not this specification.
Byte value
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
A0h
A1h
A2h
A3h
Name Length
WORD Varies
BYTE ENUM
BYTE ENUM
BYTE ENUM
WORD Varies
WORD Varies
WORD Varies
Meaning
Other
Unknown
System board
ISA add-on card
EISA add-on card
PCI add-on card
MCA add-on card
PCMCIA add-on card
Proprietary add-on card
NuBus
PC-98/C20 add-on card
PC-98/C24 add-on card
PC-98/E add-on card
PC-98/Local bus add-on card
Value
The handle, or instance number, associated with the
structure
The physical location of the Memory Array, whether on
the system board or an add-in board. See System
Management BIOS Reference Specification, v2.3.1,
section 3.3.17.1 for definitions.
Identifies the function for which the array is used. See
System Management BIOS Reference Specification,
v2.3.1, section 3.3.17.2 for definitions.
The primary hardware error correction or detection
method supported by this memory array. See System
Management BIOS Reference Specification, v2.3.1,
section 3.3.17.2 for definitions.
The maximum memory capacity, in kilobytes, for this
array. If the capacity is unknown, this field contains
8000 0000h.
The handle, or instance number, associated with any
error that was previously detected for the array. If the
system does not provide the error information structure,
the field contains FFFEh; otherwise, the field contains
either FFFFh (if no error was detected) or the handle of
the error-information structure. See also System
Management BIOS Reference Specification, v2.3.1.
The number of slots or sockets available for Memory
Devices in this array. This value represents the number
of Memory Device structures that comprise this
Memory Array. Each Memory Device has a reference to
the 'owning' Memory Array.
Description
Configur ation
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