Table of Contents
Advertisement
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bits 13:15
Interpretation of SEL format for PCI bus related errors: The following table defines
the data byte formats for PCI bus-related errors logged by the BIOS.
Field
Generator ID
7:1 System software ID or IPMB slave
address. 1=ID is system software
ID; 0=ID is IPMB slave address.
EvMRev
Event Message Revision
Sensor Type
Sensor Number
Number of sensor that generated this
event
Event Direct /
0x6F if event offsets are specific to the
Event Type
sensor
Event Data 1
7:6 00 = unspecified byte 2; 10 = OEM
code in byte 2.
5:4 00 = unspecified byte 3; 10 = OEM
code in byte 3. (BIOS will not use
encodings 01 and 11 for errors
covered by this document.).
3:0... Offset from Event Trigger for
discrete event state.
IPMI definition
Other
Unknown
Fast-paged
Static column
Pseudo-static
RAMBUS
Synchronous
CMOS
EDO
Window DRAM
Cache DRAM
Non-volatile
Reserved, set to 0
BIOS-specific implementation
7:4 0x3 for system BIOS
3:1 0
Format rev ision. Revision of the data format for
OEM data bytes 2 and 3. For this revision of the
specification, set this field to 0. All other rev isions are
reserved for now.
0
1 = ID is system software ID.
As a result, the generator ID byte will start from 0x31 and
go up to 0x3f, in increments of 2 for events logged by the
BIOS.
This field is used to identify different revisions of the
Event Message format. The rev ision number shall be 03h
for Event Messages that comply with the format given in
this specification.
0x13 for critical interrupt.
Unique value for each type of ev ent because IPMI
specification requires as such. This field has no other
significance. Should not be displayed to the end-user if
the event is logged by BIOS.
7
0= Assertion Event, 1 = Deassertion Event
6:0 0x6F
Follow IPMI definition. If either of the two data bytes
following this do not have any data, that byte should be
set to 0xff, and the appropriate field in event data 1 should
indicate that it is unspecified.
3:0 is 04 for PCI PERR and 05 for PCI SERR.
117
Configur ation
Advertisement
Table of Contents
