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When using the multi-sync mode of operation, the selection of front panel or
backplane distribution of ADC clock and SYNC signals involves the following
considerations:
•
Backplane distribution requires the use of the ECL Trigger lines on the
backplane, which are then unavailable to other modules.
•
The overall time skew between the arrival of ADC clock edges is smaller when
using backplane distribution, particularly if the master (or buffer) module is
physically located in the center of the mainframe.
•
Backplane distribution is more susceptible to pickup of jitter on the ADC clock
from other digital activity on the VXI backplane. The extent of this pickup
depends on the mainframe and on the other modules in the mainframe. One
important step in reducing this pickup is to disable, whenever possible, the 10
MHz VXI clock generated by the slot-0 controller.
•
For backplane distribution make sure that all modules conform to VXI
specification 1.4 or later with regard to their attachment to the ECL Trigger
lines. See the Technical Specifications for the clock jitter (phase noise)
specification degradation using backplane distribution.
•
Front panel distribution requires the use of two short, relatively well matched
cables with SMB connectors between modules. In addition, unused SMB
connectors on modules being used for front panel distribution must be
terminated in 50 ohms.
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E1437A User's Guide
Using the E1437A
3-9
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