Managing Multiple Modules; Clock Distribution - Agilent Technologies E1437A User Manual

20 msample/second adc with filters and fifo
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E1437A User's Guide
Using the E1437A

Managing multiple modules

The E1437 supports synchronous operation among multiple E1437s by using a
shared ADC clock and SYNC signal to drive all the modules in a system. The shared
SYNC signal is used to synchronize critical operations including arming, triggering
the beginning of data collection, setting a common phase of the local oscillator for
down conversion, and forcing concurrent output sample times whenever decimation
is used. The SYNC line transitions are constrained to not occur during the critical
(setup and hold) regions of the shared ADC clock. Thus, all modules in the group
can be assured of receiving the SYNC signal on exactly the same ADC clock cycle.
The following topics provide details on sharing clock and SYNC signals:

Clock distribution

When shared, the ADC clock and SYNC lines are distributed among modules either
on the VXI backplane using the ECL Trigger lines, or on the front panel using the
SMB Clock/Sync extender connectors. When VXI backplane distribution is used with
more than one VXI mainframe, the front panel Clock/Sync connectors can be used
to buffer the ADC clock and SYNC lines from one mainframe to another.
Since the SYNC transition timing relative to the ADC clock edges is critical, the
module driving the SYNC line should ideally be the same one identified as the
master. However, when using backplane distribution, any E1437 in the same
mainframe as the master can drive the SYNC line.
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