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9
the FIFO is equal to or greater than the block size register. Check this bit before reading
data to insure that a block of data may be transferred without fear of running out of data,
thereby holding up the Local bus or VME bus. This bit is set in block mode whenever the
module has successfully taken a block size number of samples since the most recent
trigger
10 Armed: This bit is set whenever the module is in the Trigger state, or is in the Arm
state and has satisfied its pre-trigger requirements. When this bit is set, the module
releases the VXI SYNC line. Once all modules release the SYNC line, then all modules go
to the Trigger state.
11 FIFO Overflow: This bit set when the FIFO buffer overflows in continuous mode.
12 Overload: This bit is set whenever the ADC converts a sample that exceeds the
range of the ADC. The bit is cleared when the Status register is read. Repeated ADC
errors may indicate that the module should be recalibrated.
13 Error: This bit is set whenever there is an error in the error queue. It is cleared
when the error queue is empty.
14 ModID*: A (1) in this field indicates that the module is not selected via the P2
MODID line. A (0) indicates that the module is selected by a high state on the P2
MODID line.
15 Hardware Set: This bit is set when all commands are complete and the hardware has
been set.
Effect on Active
This command does not abort any measurement in progress.
Measurement
See Also
hpe1437_init
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Measure Done: This bit is set in continuous mode whenever the size of the data in
E1437A User's Guide
VXI plug&play Programming Reference
4-57
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