Agilent Technologies E1437A User Manual page 135

E1437A
ASCII Overview and Commands
Comments:
For more details on the interaction among source, master and sync with multiple
modules and multiple mainframes see Managing multiple modules.
The master, multisync, source, and dsp parameters are interdependent with
legitimate combinations being as follows (along with the resultant DSP clock rates):
If fs>20,480,000 then dsp must = ADC
The maximum rate at which data may be transferred to memory is determined by
the DSP clock rate: Max bytes/s. = 4 * DSP clock rate. In continuous mode the
maximum rate is limited to (4 * DSP clock rate)/2. However, you may successfully
perform this type of measurement by adding a level of decimation to reduce the
sample rate.
Example: The correct method to set up a synchronous multi-module group that insures that
all modules share the same ADC clock is:
! First, insure that one module is putting its clock on the backplane
OUTPUT <addrMaster>;" CLOCK:Master
! Put each module into multi-sync mode with internal clock!
clock is connected to
! master HP E1437
! For each module address (except master):
OUTPUT <addrAll>;"Clock:Setup 2,0,1,0,20480000"
Reset State:
multisync=OFF, source=20480000, dsp=ADC, master=OFF, fs=20480000
See Also: FILTER:SETUP, DATA:SETUP
5-12
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MASTER SYNC
N/A OFF
N/A OFF
N/A OFF
N/A OFF
FRONT
OFFBUFFER
FRONT
OFFBUFFER
OFF REAR
OFF REAR
ON FRONT
ON FRONT
ON FRONT
ON FRONT
ON REAR
ON REAR
ON REAR
ON REAR
BUFFER REAR
BUFFER REAR
through Ext Clk TTL connector).
SOURCE DSP
20.x (internal) N/A
EXT ADC
EXT OSC
EXT:PLL N/A
N/A ADC
N/A OSC
N/A ADC
N/A OSC
20.x N/A
EXT ADC
EXT OSC
EXT:PLL N/A
20.x N/A
EXT ADC
EXT OSC
EXT:PLL N/A
N/A ADC
N/A OSC
1"
CLOCK:SETUP
command/query
DSP CLOCK
RATE
Internal source
External source
20.48
20
Master ADC
20.48
Master ADC
20.48
Source
External
20.48
20
Source
External
20.48
20
Master ADC
20.48
(unless external