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E1437A
ASCII Overview and Commands
STATUS?
Reads Status Register information for the module.
Query Syntax:
STATUS?
Example Statements:
OUTPUT 70924;"Status?
ENTER 70924;Result$
Parameter Definitions:
Result$ contains the status word. The bits are defined below:
1-0 State: These two bits indicate the current state of the measurement loop as shown
in the table below. See the Measurement Loop section for more information about the
states
2 Passed: This bit is always set to 1.
3 Ready: This bit is set whenever the module is operating as a message-based device
and is set for Normal operation. See the VXIbus Specifications for more information on
the Normal configuration sub-state.
4 ADC Error: This bit is set whenever a hardware error is detected in the ADC. The bit
is cleared when the Status register is read.
5 Ext Clk Speed: This bit is set when a measurement has been aborted because the
external clock is too fast (over 20.48 MHz) with respect to the DSP clock. This situation
only occurs when a fast external ADC clock is used with an internal oscillator DSP clock.
This bit is cleared with the first subsequent read.
6 Setup error: An invalid parameter value was requested. If an invalid block size was
requested, the closest valid block size is used until a change to an interrelated parameter
makes the requested block size valid. If a data resolution, data type, filter bandwidth, or
filter decimation parameter was requested which would result in an inability to make a
measurement, the previous valid parameter is used until a change to an interrelated
parameter makes the requested parameter valid.
7 Sync/Idle Complete: This bit is set when the most recent user-initiated SYNC or IDLE
change has propagated through to all modules in a system. The change is a result of
asserting SYNC or forcing IDLE via the Control Register or issuing a MEAS:CONTROL
command.
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Bits
State
11
Trigger
10
Measure
01
Arm
00
Idle
STATUS?
query
query
5-45
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