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E1437A User's Guide
Module Description
Data Formatting and FIFO Memory
The E1437A can be programmed to save the real component of the signal or to save
the complete complex signal. The data precision can be set to 16 bits or 32 bits.
Thus, each sample will occupy from two to eight bytes of memory in the FIFO. The
data formatting block packs the selected data into 64-bit words which are stored in
the FIFO memory. Since the standard FIFO depth is 1-Mword (8 MByte), it is
possible to hold up to 4-Msamples in memory at one time.
The memory may be configured either in block mode or in continuous mode. In
block mode, data collection initiated by a trigger will proceed until a specified block
length is captured. The measurement is then paused so that the data can be read
out. Before a new block can be collected, the module must be re-armed and
triggered again. This mode is useful in capturing single transient events or whenever
the output data rate is too high to be read and processed in real time.
In continuous mode, data collection is initiated by a trigger and will continue as long
as the FIFO does not overflow. Data may be read out of the memory while the
measurement is in progress. If the reading of data is sufficiently fast, the FIFO will
never overflow and the measurement will continue indefinitely. If the FIFO should
ever overflow then the measurement will stop and wait for data to be read out, the
measurement to be re-armed, and a new trigger. This mode of operation is useful for
real-time applications that employ a high speed signal processor to continuously
read and operate on each sample of data. Data can be read from the FIFO in bursts
to accommodate pauses for such things as disk access times or block mode
computations.
The effective trigger time may be offset from the actual trigger event by
programming a trigger timing offset. See the Technical Specifications for the limits
of the pre-trigger and post-trigger offset.
Data Output
There are two ways to output data from the E1437A: by way of the VXI backplane or
by way of the local bus.
To use the VXI backplane, the E1437A can be programmed so that the output of the
FIFO is sent to the Send Data register. Each 64-bit portion of the FIFO memory is
sent to the 16-bit register as four separate words. The register can then be read by
any controller compatible with the VME standard. Maximum data flow is about 2
MB/s.
The local bus allows data transfers over a high speed 8-bit ECL bus to an adjacent
module (to the right) in the VXI mainframe. Multiple adjacent E1437A modules can
send data to one signal processor module. The signal processor must be one which
supports the Hewlett-Packard ECL local bus protocol, such as the E1485A/B. In
addition to higher speed (up to 40 MB/s), the local bus has the advantage that data
can be output at the same time that control signals are being sent over the VXI
backplane.
In both of the data output modes, the samples must be read out sequentially, offset
by the trigger delay.
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