Agilent Technologies E1437A User Manual page 134

20 msample/second adc with filters and fifo
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E1437A
ASCII Overview and Commands
selects the clock used to drive the decimation/zoom section within the E1437.
Normally, the DSP clock should be coupled to the ADC clock whenever possible
since the spurious performance specification is degraded when the clocks are
independent. However, when a slow or intermittent ADC clock results in greater
than 1 µs between clock edges, the DSP clock must be generated from the internal
oscillator to avoid data loss in the dynamic RAM.
parameter
value
0
1
determines whether an E1437 makes its local ADC clock available to other
modules as a shared clock. Multi-module synchronization requires that one and only
one of the modules to be identified as the master, the source of the shared ADC
clock.
parameter
value
0
1
2*
* Only one module per mainframe may be set to 1 or to 2. In multi-mainframe systems using backplane
clock and sync distribution only one module per any mainframe not containing the master may be set to 2.
provides the module with the frequency of an external sample clock connected to
the Ext Clk TTL connector. When using an external clock or when a module is a
non-master in a multi-module group, the frequency of the ADC clock is unknown by
the module. It is the responsibility of the programmer to provide the correct
frequency so that commands dependent on fs will operate properly. This value has
no effect if the module is set up to use the internal ADC clock.
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dsp parameter definition
OSC. Causes the DSP clock to be the internally generated 20.48 MHz oscillator.
ADC. Forces the DSP clock to be driven by the ADC clock
master parameter definition
OFF. The module is driving neither the front panel nor the back plane. This is the correct
variable to use for all non-master modules in a system.
ON. When multisync=1 (front panel) the E1437 drives the front panel ADC clock.
If multisync=2 (back plane) the module uses its ADC clock to drive the VXI backplane in
the mainframe in which it resides.
BUFFER. Allows the ADC clock and SYNC lines from the module's front panel connectors
to drive the backplane of a mainframe not containing the master.
CLOCK:SETUP
command/query
5-11

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