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E1437A User's Guide
Module Description
Clock Generation
The usual source for a clock signal is the 20 MHz or the 20.48 MHz crystal oscillator
inside the E1437A. However, the E1437A can also accept an external clock signal
through a front-panel BNC ("Ext Clock"). This signal can be TTL, ECL, or sine wave.
In a system using more than one E1437A, the ADCs can be synchronized by
programming them to use a common ECL line on the backplane. One of the modules
can be the clock master that drives this line. This master clock can be extended to
other mainframes by connecting a "Clock" SMB connector to a "Clock" SMB
connector on an E1437A in the second mainframe.
HP E1437A Clock Generation
VXI
Clock
Signal
Ext
Clock
In
20.0 MHz
or
20.48 Mhz
Input Amplifier
The input amplifier provides an input termination which maintains good flatness to
8 MHz. The gain/attenuation of the input amplifier is programmable.
Under program control, the input signal can be ac coupled. This allows the system to
measure low level ac signals in the presence of a large dc offset. .
Anti-alias Filter
Since the normal ADC sample rate is 20 MHz, a complete representation of the input
signal can be achieved only for bandwidths up to 10 MHz. Frequency components
above 10 MHz can cause ambiguous results (aliasing).
The anti-alias filter attenuates these high frequency components to reduce aliasing.
The anti-alias filter in the E1437A is flat to 8 MHz and rejects signals above 12 MHz
by at least 100 dB. Thus the 0-8 MHz frequency range of the sampled signal will be
alias free. The filter's transition band from 8 MHz to 12 MHz will affect flatness and
allow some aliasing in the sampled signal frequency range of 8 MHz-10 MHz.
6-6
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Master
SMB
Multi-
Extenders
Module
Sync
ON
ADC Clock
Source
Internal Clock
Zoom,
Analog to
Filters,
Digital
FIFO
Converter
DSP
Clock
Source
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