Signal Description - Samsung S5PV210 Hardware Design Manual

S5PV210_HARDWARE DESING GUIDE REV 1.0
24. IIS MULTI AUDIO INTERFACE (v5.1)

24.1. Signal Description

Signal
I2S_0_SCLK
I2S_0_CDCLK
I2S_0_LRCK
I2S_0_SDI
I2S_0_SDO[2:0]
24.2. Audio Port
There are three IIS Interface Controllers in S5PV210. IIS channel 1,2 are for normal 2 channel IIS. You can use 5.1
channel IIS with channel 0.
External Clock Source
S5PV210 provides a master clock to the codec through the I2S_CDCLK line. This configuration has an advantage
that it is not necessary to configure oscillator circuit. For the making Master Clock, S5PV210 uses and divided
EPLL, MPLL or PCLK (refer to the User's Manual). Among these clock sources, divided EPLL is used for Lower
Power Audio especially.
If an oscillator circuit is configured for a precise clock for the Sampling Frequency without PLLs or Internal clocks,
there is a way to accept to this frequency as a source of master clock through the I2S_CDCLK line.
S5PV210 can supply 24MHz clock to Codec chip via xCLKOUT line.(refer to the User's Manual). Even at Power
down mode, this signal keep supplying to Codec chip. When Codec chip need 24MHz, external oscillator circuit can
be reduced by using this configuration.
I/O Description
IO IIS-bus serial clock for channel 0 (Lower Power Audio)
IO IIS CODEC system clock for channel 0 (Lower Power Audio)
IO IIS-bus channel select clock for channel 0 (Lower Power Audio)
I IIS-bus serial data input for channel 0 (Lower Power Audio)
O IIS-bus serial data output for channel 0 (Lower Power Audio)
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