Samsung S5PV210 Hardware Design Manual page 87

Risc microprocessor
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S5PV210_HARDWARE DESING GUIDE REV 1.0
II. CSn, CKE, ADDR[13:0], BA[1:0], RASn, CASn, WEn, AP signal
 
a) SCLK(n) & ADDR[15:0], CASn, RASn, CKE[1:0], WEn Skew: -/+ 100ps (Target length: -/+ 10mm).
b) T-branch topology is recommended for Command, Address and Control net.(CKE[1:0], CSn[1:0],
 
ADDR[15:0], RASn, CASn, WEn)
c) Do not route near high speed signals (SCLK, SCLKn, DQS(n)[3:0] and DATA net) or have enough spacing
 
over 3*WIDTH.
d) Direct connect GATEI (pin B10) to GATEO (pin C10).
 
III. SCLK, SCLKn signal
 
a) Star topology is recommenced.
b) Recommended differential impedance is 100 ohm.
 
c)SCLK & SCLKn Skew: -/+ 10ps (Target length: -/+ 1.0mm).
 
d) SCLK(n) & DQS[3:0] Skew: -/+ 100ps (Target length: -/+ 10mm).IV. Others
 
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