Samsung S5PV210 Hardware Design Manual page 86

S5PV210_HARDWARE DESING GUIDE REV 1.0
Power and ground design guide
General design rule is applied on this case.
I. Ground layer has to be placed adjacent to signal layer for current return path.
II. Ground plane has not to be split.
III. Connection of ground pins
a) Connect to ground plane through ground via as short as possible.
b) Connect ground pad of bypass capacitor to ground plane through ground via as short as possible.
c) Join together ground pins adjacent each other for making lower impedance.
IV. Connection of power pin
a) Place bypass capacitor near power pin as short as possible.
b) Connect power pad of bypass capacitor to power plane through power via as short as possible.
c) Pay attention whether power via makes ground plane split or not.
The value of bypass capacitor is determined by considering impedance profile of power plane and operating
frequency. And the number of capacitors is as large as possible considering of PCB space.
Trace routing guide
I. DQ, DQM, DQS signal
Signals in same group have pattern length matched within 1.5mm for equalizing timing skew. If signals in same
group have to be routed on different layer, impedance of the layer must be considered.
a) DQS0 & DATA[7:0], DQM0 Skew: -/+ 50ps (Target length: -/+ 5.0mm)
b) DQS1 & DATA[15:8], DQM0 Skew: -/+ 50ps (Target length: -/+ 5.0mm)
c) DQS2 & DATA[23:16], DQM0 Skew: -/+ 50ps (Target length: -/+ 5.0mm)
d) DQS3 & DATA[31:24], DQM0 Skew: -/+ 50ps (Target length: -/+ 5.0mm)
Data Group
DQ [7:0]
DQ [15:8]
DQ[23:16]
DQ[31:24]
Mask Signal
DQM0
DQM1
DQM2
DQM3
Clock
DQS0
DQS1
DQS2
DQS3
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